View ADAS3022_8329437.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

16 - bit, 1 msps, 8 - channel data acquisition system data sheet ADAS3022 rev. b document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patent s or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks ar e the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 ? 2012 C 2013 analog devices, inc. all rights reserved. technical support www.analog.com features ease of use 16 - bit , 1 msps complete data acquisition system high impedance , 8 - channel input : > 500 m differential input voltage range: 24 . 576 v max imum h igh input common - mode rejection : >100 db user - programmable input ranges channel sequencer wi th individual channel gains on - chip 4.096 v reference and buffer auxiliary input direct interface to pulsar adc inputs no latency or pipeline delay (sar architecture) serial 4 - wire , 1.8 v to 5 v spi - /sport - compatible interface lfcsp package (6 mm 6 mm) ? 4 0 c to +8 5 c industrial temperature range applications mul ti channel data acquisition and system monitoring process control power line monitoring automated test equipment instrumentation general description the ADAS3022 is a complete 16 - bit, 1 msps , successive approxi - mation C based analog - to - digital data acquisition system , which is manufactured on anal og devices, inc., proprietary i cmos? high voltage industrial process technology . the device in tegrates an 8 - channel, low leakage multiplexer; a high impedance program - mable gain instrumentation amplifier (pgia) stage with high common - mode rejection ; a prec ision, low drift 4.096 v reference and buffer; and a 16 - bit charge redistribution analog - to - digital converter (adc) with successive approximation register (sar) architecture. t he ADAS3022 can resolve eight single - ended inputs or four fully differential inputs up to 24.576 v when using 15 v supplies . in addition, t he device can accept the commonly u sed bipolar differential, bipolar single - ended, pseudo bipolar, or pseudo unipolar input signal s , as shown in table 1 , thus enabling the use of almost any direct sensor interface. t he ADAS3022 s implifies design challenges by eliminating signal buffering , level shifting, amplification /attenuation , common - mode rejection , settli ng time, and any other analog signal conditioning challenge while allowing a smaller form factor, faster time to market , and lower cost . table 1 . typical input range selection signal input range, v in differential 1 v 1.28 v 2 .5 v 2.56 v 5 v 5.12 v 10 v 10.24 v single ended 1 0 v to 1 v 1.28 v 0 v to 2.5 v 2.56 v 0 v to 5 v 5.12 v 0 v to 10 v 10.24 v 1 se e figure 59 and figure 60 in the analog inputs section for more information. functional block dia gram in4 in5 in3 in2 buf in6 in7 in1 in0 in0/in1 pair diff to diff com in2/in3 in4/in5 in6/in7 pulsar adc logic/ interface refin ref refx cnv reset pd sck din sdo vssh vddh agnd vio dvdd avdd dgnd cs com aux+ aux? busy ADAS3022 mux temp sensor 10516-001 pgia figure 1.
important links for the ADAS3022 * last content update 11/13/2013 12:20 pm similar products & parametric selection tables find similar products by operating parameters video: ADAS3022 16-bit 1msps daq high resolution - simultaneous sampling14/16/18-bit pulsar adcs high resolution - muxed 14/16-bit pulsar adcs documentation cn0201: complete 5 v, single-supply, 8-channel multiplexed data acquisition system with pgia for industrial signal levels ug-484: evaluation board for the ADAS3022 16-bit, 8-channel, 1 msps data acquisition system complete sensor-to-bits solution simplifies industrial data- acquisition system design sensor-to-bits: simplifying daq design analog devices data acquisition ic simplifies industrial and instrumentation equipment design design tools, models, drivers & software ADAS3022 fpga reference design ADAS3022/adas3023 ibis model design support submit your support request here: linear and data converters embedded processing and dsp telephone our customer interaction centers toll free: americas: 1-800-262-5643 europe: 00800-266-822-82 china: 4006-100-006 india: 1800-419-0108 russia: 8-800-555-45-90 quality and reliability lead(pb)-free data sample & buy ADAS3022 view price & packaging request evaluation board request samples check inventory & purchase find local distributors evaluation kits & symbols & footprints view the evaluation boards and kits symbols and footprints suggested companion products recommended driver amplifiers for the ADAS3022 for low frequency, precision, low bias current applications, we recommend the ad8476, ad8605, or the ad8615 . for precision, low power, low distortion applications, we recommend the ada4841-1, ada4940-1 or the ada4941-1 . for high frequency, low noise, low distortion applications, we recommend the ada4899, ada4897-1, or the ad8021 . for additional driver amplifier selections , we recommend selecting the product category and filtering on our parametric search tables. recommended external voltage references for the ADAS3022 for low drift, low noise and high accuracy, we recommend the adr434, adr444 or the adr4540 (4.096v) references. for driving the voltage reference input, we recommend the ad8031 or the ad8605 buffer amplifiers. for additional voltage reference selections , we recommend filtering on our parametric search tables. recommended digital isolators for the ADAS3022 for spi interface, lowest power, 2.5 kvrms isolation, we recommend the adum1401 . for spi interface, enhanced system-level esd performance, 2.5 kvrms isolation, we recommend the adum3401 . for spi interface, low power, 5.0 kvrms isolation, we recommend the adum4401 . for spi interface, smallest package, low voltage i/o (1.8 v to 5.5 v), we recommend the adum3481 . for additional digital isolator selections , we recommend filtering on our parametric search tables. recommended low dropout regulators and switchers for the ADAS3022 for avdd, dvdd and vio, we recommend the adp3334, adp1715, adp7102 or the adp7104 . for vddh and vssh, we recommend the adp1613 or the adp1614 . for additional regulator and switcher selections , we recommend selecting the product category and filtering on our parametric search tables. design collaboration community collaborate online with the adi support team and other designers about select adi products. * this page was dynamically generated by analog devices, inc. and inserted into this data sheet. note: dynamic changes to the content on this page (labeled 'important links') does not constitute a change to the revision number of the product data sheet. this content may be frequently modified. powered by tcpdf (www.tcpdf.org)
ADAS3022 data sheet rev. b | page 2 of 40 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 general description ......................................................................... 1 functional block diagram .............................................................. 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 timing specifications .................................................................. 7 absolute maximum ratings ............................................................ 9 esd caution .................................................................................. 9 pin configuration and function descriptions ........................... 10 typical performance characteristics ........................................... 12 terminology .................................................................................... 20 theory of operation ...................................................................... 22 overview ...................................................................................... 22 ADAS3022 operation ................................................................ 22 transfer function ....................................................................... 23 typical application connection diagram .............................. 24 analog inputs .............................................................................. 25 voltage reference output/input .............................................. 28 power supply ............................................................................... 29 conversion modes ..................................................................... 30 digital interface .............................................................................. 31 conversion control ................................................................... 31 reset and power - d own (pd) inputs ....................................... 32 serial data interface ................................................................... 32 general considerations ............................................................. 33 general timing ........................................................................... 34 configuration register .............................................................. 36 channel sequencer details ....................................................... 37 outline dimensions ....................................................................... 39 ordering guide .......................................................................... 39 revision history 4 / 13 rev. a to rev. b changes to table 1 ............................................................................ 1 added input impedance of 500 m min , table 2 ....................... 3 1 / 13 rev. 0 to rev. a removed endnote 3 and added t a = 25c to gain error te st conditions/comments , table 2 ...................................................... 3 changes to ref1 and ref2 description ..................................... 11 added figure 25 to figure 28 ; renumbered sequentially ........ 15 changes to figure 29 ...................................................................... 15 added f igure 30 .............................................................................. 16 changes to figure 33 , figure 34 , and figure 35 ......................... 16 changes to figure 36 and figure 37 ............................................. 17 changes to figure 50 ...................................................................... 19 changes to figure 54 ...................................................................... 24 changes to figure 56 ...................................................................... 2 5 changes to figure 57 , figure 58 , figure 59 , and figure 60 ....... 2 6 changes to voltage refe rence output/input section, figure 62 , and figure 63 ................................................................................... 2 8 changes to core supplies section ................................................ 29 11 /12 revision 0: initial version
data sheet ADAS3022 rev. b | page 3 of 40 specifications vdd h = 15 v 5% , vss h = ?15 v 5% , a vdd = dvdd = 5 v 5% , v io = 1 .8 v to av dd , internal reference, v ref = 4. 096 v , f s = 1 msps . a ll specifications t min to t max , unless otherwise noted. table 2 . parameter test conditions/comments min typ max unit 1 resol ution 16 bits analog inputs in[7:0], com operating input voltage range v in ? vssh + 2.5 vddh ? 2.5 v differential input voltage range , v in v in+ ? v in? pgia gain = 0.16 , v in = 49.15 v p -p ?6v ref +6v ref v pgia gain = 0.2 , v in = 40.96 v p -p ?5v ref +5v ref v pgia gain = 0.4 , v in = 20.48 v p -p ?2.5v ref +2.5v ref v pgia gain = 0.8 , v in = 10.24 v p -p ?1.25v ref +1.25v ref v pgia gain = 1.6 , v in = 5.12 v p - p ?0.625v ref +0.625v ref v pgia gain = 3.2 , v in = 2.56 v p -p ?0.3125v ref +0.3 125v ref v pgia gain = 6.4 , v in = 1.28 v p -p ?0.1563v ref +0.1563v ref v input impedance z in 500 m channel off leakage 0.6 na channel on leakage 0.02 na common - mode voltage range 2 v in+ , v in? ; full - scale differential inputs pgia gain = 0.4 ?5.12 +5.12 v pgia gain = 0.8 ?7.68 +7.68 v pgia gain = 1.6 ?8.96 +8.96 v pgia gain = 3.2 ?9.60 +9.60 v pgia gain = 6.4 ?9.92 +9.92 v analog inputs aux +, aux? differential input voltage range ?v ref +v ref v throughput con version rate one channel/ one pair 0 100 0 ksps two channels/two pairs 0 500 ksps four channels/four pairs 0 250 ksps eight channels 0 125 ksps transient response full - scale step 5 2 0 ns dc accuracy no missing codes 16 bits integral li nearity error pgia gain = 0.16, 0.2, 0.4, 0.8, 1.6 ? 2 0.6 + 2 lsb pgia gain = 3.2 ?3 1.0 +3 lsb pgia gain = 6.4 ?5 1.5 +5 lsb differential linearity error pgia gain = 0.16, 0.2, 0.4, 0.8, 1.6 ?0.9 0.6 +1.0 lsb pgia gain = 3.2 ?0.9 0.75 +1 . 25 lsb pgia gain = 6.4 ?0.9 0.75 +1 . 25 lsb transition noise external reference pgia gain = 0.16, 0.2, 0.4, 0.8, 1.6 5 lsb pgia gain = 3.2 7 lsb pgia gain = 6. 4 11 lsb gain error external reference , all pgia gains , t a = 25c ?9 +9 lsb gain error temperature drift external reference , all pgi a gains 0.1 ppm/c offset error external reference, t a = 25c pgia gain = 0.16 , 0.2, 0.4, 0.8 ?3.0 +0.2 +3.0 lsb pgia gain = 1.6 ?4.0 +0.2 +4.0 lsb pgia gain = 3.2 ?7.5 +0.2 +7.5 lsb pgia gain = 6.4 ?12.5 +0.2 +12.5 lsb
ADAS3022 data sheet rev. b | page 4 of 40 parameter test conditions/comments min typ max unit 1 offset error tempera ture drift external reference pgia gain = 0.16 , 0.2, 0.4, 0.8 0.1 0. 5 ppm/c pgia gain = 1.6 0.2 1.0 ppm/c pgia gain = 3.2 0.4 2.0 ppm/c pgia gain = 6.4 0.8 4.0 ppm/c total unadjusted error external reference, t a = 25c pgia gain = 0.16 , 0.2, 0.4, 0.8, 1.6, 3.2 ?9 +9 lsb pgia gain = 6.4 ?15 +15 lsb ac accuracy 3 signal -to - noise ratio (snr) f in = 1 0 khz pgia gain = 0.16 90.0 91.5 db pgia gain = 0.2 90.0 91.5 db pgia gain = 0.4 89.5 9 1.5 db pgia gain = 0.8 89.0 91.0 db pgia gain = 1.6 88.0 89.7 db pgia gain = 3.2 86.0 8 6.8 db pgia gain = 6.4 83.0 84. 5 db signal -to - noise - and - distortion (sinad) f in = 10 khz pgia gain = 0.16 88.0 90.0 db pgia gain = 0.2 88.0 90.0 db pgia gain = 0.4 88.5 91.0 db pgia gain = 0.8 88.5 90. 5 db pgia gain = 1.6 87.5 89.5 db pgia gain = 3.2 85.5 86.5 db pgia gain = 6.4 82.5 84.0 db dynamic range f in = 1 0 khz, ?60 db input pgia gain = 0.16 91.0 92.0 db pgia gain = 0.2 91.0 92.0 db pgia gain = 0.4 90.5 91.5 db pgia gain = 0.8 90.0 91.0 db pgia gain = 1.6 89.0 9 0 . 0 db pgia gain = 3.2 86.0 87.0 db pgia gain = 6.4 83.5 85.0 db total harmonic distortion f in = 1 0 khz , all pgia gains ?100 db spurious - free dynamic range f in = 1 0 khz , all pgia gains 101 db channel - to - channel crosstalk f in = 10 khz , all channels inactive ? 120 db common - mode rejection ratio (cmrr) f in = 2 khz pgia gain = 0.16, 0.2, 0.4 , 0.8 90.0 110.0 db pgia gain = 1.6 90.0 105.0 db pgia gain = 3.2 90.0 98.0 db pgia gain = 6.4 90.0 98.0 db ?3 db input bandwidth ?40 dbfs 8 m hz auxiliary adc input channel dc accuracy external reference integral nonlinearity error ?1.5 0.5 +1.5 lsb differential nonlinearity error ?0.8 0.6 +1.0 lsb gain error ?2.5 0.2 +2.5 lsb offset e rr or ?5 0.2 +5 lsb
data sheet ADAS3022 rev. b | page 5 of 40 parameter test conditions/comments min typ max unit 1 ac performance internal reference signal -to - noise ratio (snr) 90.0 93.0 db signal -to - noise - and - distortion (sinad) 89.5 92.5 db total harmonic distortion ?105 db spurious - free dynamic range (sfdr) 110 db internal reference ref x output voltage t a = 25c 4.088 4.096 4.104 v ref x output current t a = 25c 250 a ref x tempe rature drift refen = 1 5 ppm/c refen = 0 1 ppm/c ref x line regulation avdd = 5 v 5% internal reference 20 v/v buffer only 4 v/v refin output voltage 4 t a = 25c 2.495 2.500 2.505 v turn - on settling time c refin , c ref1 , c ref2 = 10 f and 0.1 f 100 ms external reference voltage range ref x input 4.000 4.096 4.104 v refin input (buffered) 2.5 2.505 v current drain v ref = 4.096 v 100 a tempe rature sensor output voltage t a = 25 c 275 mv temperature sensiti vity 800 v/c digital inputs logic levels v il vio > 3 v ?0.3 +0.3 vio v v ih vio > 3 v 0.7 vio vio + 0.3 v v il vio 3 v ?0.3 +0.1 vio v v ih vio 3 v 0.9 vio vio + 0.3 v i il ?1 +1 a i ih ?1 +1 a digital outputs 5 data format twos complement v ol i sink = +500 a 0.4 v v oh i source = ?500 a vio ? 0.3 v power supplies pd = 0 vio 1.8 avdd + 0.3 v avdd 4.75 5 5.25 v dvdd 4.75 5 5.25 v vddh 6 vddh > input voltage + 2.5 v 14.25 15 15.75 v vssh 6 vssh < input voltage ? 2.5 v ?15.75 ?15 ? 14.25 v i vddh pgia gain = 0.16 3.0 3. 5 ma pgia gain = 0.2 3.0 3. 5 ma pgia gain = 0.4 3.5 4 .0 ma pgia gain = 0.8 5. 0 5.5 ma pgia gain = 1.6 8.5 9.5 ma pgia gain = 3.2 15.5 17.5 ma pgia gain = 6.4 15.5 17.5 ma all pgia gains, pd = 1 100 a
ADAS3022 data sheet rev. b | page 6 of 40 parameter test conditions/comments min typ max unit 1 i vssh pgia gain = 0.16 ?3.0 ? 2.5 ma pgia gain = 0.2 ?3.0 ? 2.5 ma pgia gain = 0.4 ?3.5 ? 3 .0 ma pgia gain = 0.8 ?5.5 ? 4.5 ma pgia gain = 1.6 ?9.5 ? 8 .0 ma pgia gain = 3.2 ?17.5 ? 15 ma pgia gain = 6.4 ?17.5 ? 15 ma all pgia gains, pd = 1 10 a i avdd pgia gain = 6.4, reference buffer enabled 18 21.0 ma all other pgia gains, reference buffer enabled 16 19.0 ma pgia gain = 6.4, reference buffer disabled 14 1 7.5 ma all other pgia gains, reference buffer disabled 12 16.0 ma all pgia gains, pd = 1 100 a i dvdd all pgia gains, pd = 0 2.5 3.5 ma all pgia gains, pd = 1 10 a i vio v io = 3.3 v, pd = 0 0.3 0 1.2 ma pd = 1 10 a power supply sensitiv ity at t a = 25c external reference pgia gain = 0.16, 0.2, 0.4, 0.8; vddh/vssh 5% 0.5 lsb pgia gain = 3.2, vddh/vssh 5% 1.0 lsb pgia gain = 6.4, vddh/vssh 5% 2.0 lsb pgia gain = 0.16, avdd/dvdd 5% 0.6 lsb pgia gain = 0.2, avdd/dvdd 5% 0.8 lsb pgia gain = 0.4, avdd/dvdd 5% 1.0 lsb pgia gain = 0.8, avdd/dvdd 5% 1.5 lsb pgia gain = 1.6, avdd/dvdd 5% 2.0 lsb pgia gain = 3.2, avdd/dvdd 5% 3.5 lsb pgia gain = 6.4, avdd/dvdd 5% 7.0 lsb temperature range specified performance t min to t max ?40 +85 c 1 lsb means least significan t bit and change s depending on the voltage range. see t he programmable gain section for the lsb size. 2 the common - mode voltage (v cm ) range for a pgia gain of 0.16 or 0.2 is 0 v. 3 all ac accuracy specifications expressed in decibels are referr ed to a full - scale input fsr and tested with an input signal at 0.5 db below full scale, unless otherwise specified. 4 this is the output from the internal band gap reference. 5 there is no pipeline delay. conversion results are available immediately after a conversion is complete. 6 the differential input common - mode voltage (v cm ) range changes according to the maximum input range selected and the high voltage power supplies (vddh and vssh). note tha t the specified operating input voltage of any input pin requires 2.5 v of headroom from the vddh and vssh supplies; therefor e, (vssh + 2.5 v) inx/com (vddh ? 2.5 v).
data sheet ADAS3022 rev. b | page 7 of 40 timing specifications vddh = 15 v 5%, vssh = ?15 v 5%, avdd = dvdd = 5 v 5%, vio = 1.8 v to avdd, internal reference, v ref = 4.096 v, f s = 1 msps. all specifications t min to t max , unless otherwise noted. table 3. parameter symbol min typ max unit time between conversions t cyc warp mode, 1 cms = 0 1 1000 s normal mode (default), cms = 1 1.1 s conversion time: cnv rising edge to data available t conv warp mode, cms = 0 825 ns normal mode (default), cms = 1 925 1000 ns auxiliary adc input channel acquisition time t acq 600 ns cnv pulse width t ch 10 ns cnv high to hold time (aperture delay) t ad 2 ns cnv high to busy delay t cbd 520 ns safe data access time during conversion t ddc 500 ns quiet conversion time (busy high) t quiet warp mode, cms = 0 400 ns normal mode (default), cms = 1 500 ns data access during quiet conversion time t ddca warp mode, cms = 0 200 ns normal mode (default), cms = 1 300 ns sck period t sck 15 ns sck low time t sckl 5 ns sck high time t sckh 5 ns sck falling edge to data valid t sdoh 4 ns sck falling edge to data valid delay t sdod vio > 4.5 v 12 ns vio > 3.0 v 18 ns vio > 2.7 v 24 ns vio > 2.3 v 25 ns vio > 1.8 v 37 ns cs /reset/pd low to sdo t en vio > 4.5 v 15 ns vio > 3.0 v 16 ns vio > 2.7 v 18 ns vio > 2.3 v 23 ns vio > 1.8 v 28 ns cs /reset/pd high to sdo high impedance t dis 2 5 n s din valid setup time from sck rising edge t dins 4 ns din valid hold time from sck rising edge t dinh 4 ns cnv rising to cs t ccs 5 ns reset/pd high pulse t rh 5 ns 1 exceeding the maximum time has an effect on the accuracy of the conversion (see the conversion modes section). i ol 500a 500a i oh 1.4v t osdo c l 50pf 10516-002 figure 2. load circuit fo r digital interface timing 3 0% vio 70% vio 2v or vio ? 0.5v 1 0.8v or 0.5v 2 0.8v or 0.5v 2 2v or vio ? 0.5v 1 t delay t delay 1 2v if vio > 2.5v; vio ? 0.5v if vio < 2.5v. 2 0.8v if vio > 2.5v; 0.5v if vio < 2.5v. 10516-003 figure 3. voltage levels for timing
ADAS3022 data sheet rev. b | page 8 of 40 acquisition (n) undefined phase power up conversion (n ? 1) undefined cnv busy din cs sdo notes 1. data access can occur during a conversion ( t ddc ), after a conversion ( t dac ), or both during and after a conversion. the conversion result and the cfg regi ster are updated at the end of a conversion (eoc). 2. data access can also occur up to t ddca while busy is active (see the digital interface section for details). all of the busy time can be used to acquire data. 3. a total of 16 sck falling edges is required for a conversion result. an additional 16 edges are required to read back the cfg result associated with the current conversion. 4. cs can be held low or connected to cnv. cs with full independent control is shown in this figure. 5. for optimal performance, data access should not occur during the sampling edge. a minimum time of the aperture delay ( t ad ) should elapse prior to data access. data invalid sck 1 1 1 16/32 16 16 x 16 note 3 note 1 note 2 note 2 note 1 note 4 note 5 cfg invalid cfg (n + 2) data (n ? 1) invalid acquisition (n + 1) undefined conversion (n) undefined data (n ? 1) invalid cfg (n + 2) cfg (n + 3) data (n) invalid acquisition (n + 2) conversion (n + 1) undefined data (n) invalid cfg (n + 3) cfg (n + 4) data (n + 1) invalid acquisition (n + 3) phase conversion (n + 2) cnv busy din cs sdo data (n + 1) invalid sck 1 1 cfg (n + 4) cfg (n + 5) data (n + 2) acquisition (n + 4) conversion (n + 3) data (n + 2) cfg (n + 5) cfg (n + 6) data (n + 3) conversion (n + 4) data (n + 3) cfg (n + 6) eoc eoc eoc eoc eoc soc soc t ddc t cyc t quiet t dac t acq t ad t ddca 10516-028 figure 4. general timing diagram
data sheet ADAS3022 rev. b | page 9 of 40 absolute maximum rat ings table 4 . parameter rating analog inputs/outputs inx, com to agnd vssh ? 0.3 v to vddh + 0.3 v aux+, aux? to agnd ?0.3 v to avdd + 0.3 v ref x to agnd agnd ? 0.3 v to avdd + 0.3 v refin to agnd agnd ?0.3 v to +2.7 v refn to agnd 0.3 v ground voltage differences agnd, rgnd, dgnd 0.3 v supply voltages vddh to ag nd ? 0.3 v to +16.5 v vssh to a gnd +0.3 v to ?16.5 v avdd, dvdd, vio to agnd ?0.3 v to +7 v acap, dcap, rcap to gnd ?0.3 v to + 2.7 v digital inputs/outputs cnv, din, sck, reset, pd, cs to dgnd ?0.3 v to vio + 0.3 v sdo, busy to dgnd ?0.3 v to vio + 0.3 v internal power dissipation 2 w junction temperature 125c storage temperature range ?65c to +125c ja thermal impedance 44.1 c/w jc thermal impedance 0.28 c/w stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution
ADAS3022 data sheet rev. b | page 10 of 40 pin configuration an d function descripti ons notes 1. nc = no connect. this pin is not internally connected. 2. the exposed paddle should be connected to vssh. p i n 1 i nd i c a t o r in0 1 30 nc 40 aux? 39 vddh 38 vssh 37 refn 36 refn 35 rgnd 34 ref2 33 ref1 32 refin 31 rcap 29 nc 28 avdd 27 dvdd 26 acap 25 dcap 24 agnd 23 agnd 22 dgnd 21 dgnd in1 2 in2 3 in3 4 aux+ 5 in4 6 in5 7 in6 8 in7 9 com 10 cs 11 din 12 reset 13 pd 15 vio 17 sck 16 sdo 18 busy 19 cnv 20 nc 14 ADAS3022 top view (not to scale) 10516-004 figure 5. pin configuration table 5 . pin function descriptions pin no . m nemonic type 1 description 1 to 4 in0 to in3 ai input channel 0 to input channel 3 . 5 aux+ ai auxiliary input channel positive input. 6 to 9 in4 to in7 ai input channel 4 to input channel 7. 10 com ai in[7:0] common channel input. the in[7:0] input c hannels can be referenced to a common point . the maximum voltage on this pin is 10.24 v for all pgia gains except for a pgia gain of 0.16 , in which case the maximum voltage on this pin is 12.228 v . aux + and aux? are not referenced to com. 11 cs di chip select. active low signal. e nables the digital interface for writing and reading data. use this pin when sharing the serial bus. for a dedicated ADAS3022 serial interface , cs can be tied to dgnd or cnv to simplify the interface. 12 din di data input. serial data input used for writing the 16 - bit configuration word (cfg) that is latched on sck rising edges. cfg is an internal register that is update d on the rising edge of the end of a conversion , which is the falling edge of busy . the configuration register can be written to during and after a conversion. 13 reset di asynchronous reset. a low -to - high transition resets the ADAS3022 . the current conversion, if active, is aborted and cfg is reset to the default state. 14 , 29 , 30 nc nc no connect. this pin is not connected internally . 15 pd di p ower - down. a low -to - high transition powers down the ADAS3022 , minimizing the bias current. note that this pin must be held high until the user is ready to power on the device ; after powering on the device, t he user must wait 100 ms until the reference is enabl ed and then wait for the completion of two dummy conversions before the device is ready to convert . see the power - down mode section for more information . 16 sck di serial clock input. the din and sdo data sent to and from the ADAS3022 are synchronized with sck. 17 vio p digital interface supply. nominally , this supply should be at the same voltage as the supply of the ho st interface : 1.8 v, 2.5 v, 3.3 v, or 5 v. 18 sdo do serial data output. the conversion result is output on this pin and is synchronized to sck falling edges . the conversion result is output in two s complement format . 19 busy do busy output. an active high signal on this pin indicates that a conversion is in process . reading or writing data during the quiet conversion phase (t quiet ) may cause incorrect bit decisions. 2 0 cnv di convert input. a conversion is initiated on the rising edge of this pin . 2 1 , 22 dgnd p digital ground. connect these pins to the system digital ground plane. 23 , 24 agnd p analog ground. connect these pins to the system analog ground plane. 25 dcap p internal 2.5 v digital regulator output. decouple this internally regulated ou tput using a 10 f capacitor and a 0.1 f local capacitor . 26 acap p internal 2.5 v analog regulator output. this regulator supplies power to the internal adc core and all of the supporting analog circuits with the exception of the internal refere nce. de couple this internally regulated output using a 10 f capacitor and a 0.1 f local capacitor .
data sheet ADAS3022 rev. b | page 11 of 40 pin no . m nemonic type 1 description 27 dvdd p digital 5 v supply. decouple this supply using a 10 f capacitor and a 0.1 f local capacitor. 28 avdd p analog 5 v supply. decouple this supply using a 10 f capacitor and a 0.1 f local capacitor. 31 rcap p internal 2.5 v analog regulator output. this regulator supplies power to the internal reference. decouple this pin using a 1 f capacitor connected to r cap and a 0.1 f local capacitor. 32 refin ai/o internal 2.5 v band gap reference output , reference buffer input , or reference power - down input . see the voltage reference input/output section for more information. 3 3, 34 ref 1, ref2 ai/o reference input /output . regardless of the reference method, t h ese pin s need individual decoupling using external 10 f ceramic capacitor s connected as close to ref 1 , ref2 , and refn as possible . s ee the voltage reference output/input section for more information. ref1 and ref2 must be tied together externally. 35 rgnd p reference supply ground. connect this pin to the system analog ground plane. 36, 37 refn p reference input/output ground. connect t he 10 f capacitors on ref1 and ref2 to these pins , and connect these pins to the system a nalog ground plane. 38 vssh p high voltage analog negative supply. nominally , the supply of this pin should be ? 15 v. decouple this pin using a 10 f capacitor and a 0.1 f local capacitor. 39 vddh p high voltage analog positive supply. nominally , the supply of this pin should be + 15 v . decouple this pin using a 10 f capacitor and a 0.1 f local capacitor. 40 aux ? ai auxiliary input channel negative input. epad exposed paddle. the exposed paddle should be connected to vssh. 1 ai = a nalog i nput, ai/o = analog input/output, di = d igital i nput, do = d igit al o utput, and p = p ower .
ADAS3022 data sheet rev. b | page 12 of 40 typical performance characteristics vddh = 15 v, vssh = ?15 v, avdd = dvdd = 5 v, vio = 1.8 v to avdd, unless otherwise noted. 0 8192 16384 24576 32768 code 40960 49152 57344 65536 in l (lsb) g ain = 0.16, 0.2, 0.4, 0.8, 1.6 in l max = 0.649 in l min = ?0.592 10516-101 ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 1.0 1.5 2.0 figure 6. integral nonlinearity vs. code, pgia gain = 0.16, 0.2 , 0.4, 0.8 , and 1.6 ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 1.0 1.5 2.0 0 8192 16384 24576 32768 code 40960 49152 57344 65536 in l (lsb) 10516-105 g ain = 3.2 in l max = 1.026 in l min = ?0.948 figure 7. integral nonlinearity vs. code, pgia gain = 3.2 ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 1.0 1.5 2.0 0 8192 16384 24576 32768 code 40960 49152 57344 65536 in l (lsb) 10516-106 g ain = 6.4 in l max = 0.558 in l min = ?1.319 figure 8. integral nonlinearity vs. code, pgia gain = 6.4 ?1.00 ?0.75 ?0.50 ?0.25 0 0.25 0.50 0.75 1.00 0 8192 16384 24576 32768 code 40960 49152 57344 65536 dn l (lsb) for al l gains 10516-108 figure 9. differential nonlinearity vs. code for all pgia gains 0 50,000 100,000 150,000 200,000 250,000 300,000 350,000 400,000 7ffc 7ffd 7ffe 7fff 8000 8001 8002 8003 8004 8005 8006 8007 8008 8009 count code in hex gain = 0.16, 0.2, 0.4, 0.8, 1.6 10516- 1 17 600 52,300 300,200 152,600 6,400 figure 10 . histogram of a dc input at code center, pgia gain = 0.16, 0.2, 0.4, 0.8 , and 1.6 0 50,000 100,000 150,000 200,000 250,000 300,000 350,000 400,000 7ffc 7ffd 7ffe 7fff 8000 8001 8002 8003 8004 8005 8006 8007 8008 8009 count code in hex 10516- 1 19 gain = 3.2 1 ,400 22 ,700 118 ,400 213 ,200 129 ,000 25 ,500 1 ,600 figure 11 . histogram of a dc input at code center, pgia gain = 3.2
data sheet ADAS3022 rev. b | page 13 of 40 0 50,000 100,000 150,000 200,000 250,000 300,000 350,000 400,000 7ffc 7ffd 7ffe 7fff 8000 8001 8002 8003 8004 8005 8006 8007 8008 8009 count code in hex 10516-120 gain = 6.4 300 200 21,700 82,000 157,300 151,900 75,100 18,400 2,400 100 figure 12 . histogram of a dc input at code center, pgia gain = 6.4 0 10 20 30 40 50 60 70 80 90 100 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 count offset drift (ppm/c) ex t e rn a l r e f e r e n c e gain = 0.16, 0.2, 0.4, 0.8, 1.6 f s = 1000 k sp s 10516-155 figure 13 . offset drift, pgia gain = 0.16, 0.2, 0.4, 0.8, and 1.6 0 10 20 30 40 50 60 70 80 90 100 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 count offset drift (ppm/c) ex te rn a l re fe re nc e gain = 3.2 f s = 1000 ksp s 10516-156 figure 14 . offset drift, pgia gain = 3.2 0 10 20 30 40 50 60 70 80 90 100 0 0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6 4.0 count offset drift (ppm/c) ex t e rn a l r e f e r e n c e gain = 6.4 f s = 1000 k sp s 10516-157 figure 15 . offset drift, pgia gain = 6.4 112 72 23 2 0 20 40 60 80 100 120 0 1 2 3 4 5 6 7 8 9 10 count reference buffer drift (ppm/c) f s = 1000 ksps ex t e r n a l 2 . 5 v r e f e r e n ce i n t e r n a l b u ff e r 10516-140 figure 16 . re ference buffer drift, external reference 46 35 30 15 15 11 10 6 2 1 0 20 40 60 80 100 120 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 count reference buffer drift (ppm/c) 38 f s = 1000 ksps in t e r n a l 2 . 5 v r e f e r e n ce i n t e r n a l b u ff e r 10516-141 figure 17 . reference buffer drift, internal reference
ADAS3022 data sheet rev. b | page 14 of 40 ?180 ?160 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 0 100 200 300 400 500 amplitude (dbfs) frequency (khz) gain = 0.16 f s = 1000ksps f in = 10.1khz snr = 91.7db sinad = 89.2db thd = ?92.5db sfdr = 92.5db 10516-121 figure 18 . 10 khz fft, pgia gain = 0.16 ?180 ?160 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 0 100 200 300 400 500 amplitude (dbfs) frequency (khz) gain = 0.2 f s = 1000ksps f in = 10.1khz snr = 91.4db sinad = 89.9db thd = ?94.7db sfdr = 94.8db 10516-122 figure 19 . 10 khz fft, pgia gain = 0.2 ?180 ?160 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 0 100 200 300 400 500 amplitude (dbfs) frequency (khz) gain = 0.4 f s = 1000ksps f in = 10.1khz snr = 91.2db sinad = 91.0db thd = ?103db sfdr = 104db 10516-123 figure 20 . 10 khz fft, pgia gain = 0.4 ?180 ?160 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 0 100 200 300 400 500 amplitude (dbfs) frequency (khz) gain = 0.8 f s = 1000ksps f in = 10.1khz snr = 90.7db sinad = 90.6db thd = ?107db sfdr = 106db 10516-124 figure 21 . 10 khz fft, pgia gain = 0.8 ?180 ?160 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 0 100 200 300 400 500 amplitude (dbfs) frequency (khz) gain = 1.6 f s = 1000ksps f in = 10.1khz snr = 89.8db sinad = 89.7db thd = ?106db sfdr = 107db 10516-125 figure 22 . 10 khz fft, pgia gain = 1.6 ?180 ?160 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 0 100 200 300 400 500 amplitude (dbfs) frequency (khz) gain = 3.2 f s = 1000ksps f in = 10.1khz snr = 87.6db sinad = 87.5db thd = ?105db sfdr = 106db 10516-126 figure 23 . 10 khz fft, pgia gain = 3.2
data sheet ADAS3022 rev. b | page 15 of 40 ?180 ?160 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 0 100 200 300 400 500 amplitude (dbfs) frequency (khz) gain = 6.4 f s = 1000ksps f in = 10.1khz snr = 85.7db sinad = 85.6db thd = ?101db sfdr = 103db 10516-127 figure 24 . 10 khz fft, pgia gain = 6.4 10516-303 100 95 90 85 80 75 70 1 1000 100 10 snr (db) frequency (khz) gain = 0.4, ?0.5dbfs gain = 0.8, ?0.5dbfs gain = 1.6, ?0.5dbfs gain = 3.2, ?0.5dbfs gain = 0.4, ?10dbfs gain = 0.8, ?10dbfs gain = 1.6, ?10dbfs gain = 3.2, ?10dbfs figure 25 . snr vs. frequency 10516-302 100 95 90 85 80 75 70 65 60 55 50 1 1000 100 10 sinad (db) frequency (khz) gain = 0.4, ?0.5dbfs gain = 0.8, ?0.5dbfs gain = 1.6, ?0.5dbfs gain = 3.2, ?0.5dbfs gain = 0.4, ?10dbfs gain = 0.8, ?10dbfs gain = 1.6, ?10dbfs gain = 3.2, ?10dbfs figure 26 . sinad vs. frequency 10516-304 ?55 ?60 ?65 ?70 ?75 ?80 ?85 ?90 ?95 ?100 ?105 ?110 ?115 ?120 ?125 1 1000 100 10 thd (db) frequency (khz) gain = 0.4, ?0.5dbfs gain = 0.8, ?0.5dbfs gain = 1.6, ?0.5dbfs gain = 3.2, ?0.5dbfs gain = 0.4, ?10dbfs gain = 0.8, ?10dbfs gain = 1.6, ?10dbfs gain = 3.2, ?10dbfs figure 27 . thd vs. f requency 10516-300 ?60 ?70 ?80 ?90 ?100 ?110 ?120 ?130 ?140 0 20 40 60 80 100 120 140 160 180 200 crosstalk (db) frequency (khz) internal reference channel 4 to com, sequencer disabled vin = ?0.5dbfs on channels 0 to 3, 5 to 7 f s = 1000ksps figure 28 . crosstalk vs. frequency 60 70 80 90 100 110 120 130 1 10 100 1k 10k 100k cmrr (db) frequency (hz) common-mode amplitude = 20.48v p-p internal reference f s = 1000ksps gain = 0.16 gain = 0.20 gain = 0.40 gain = 0.80 gain = 1.60 gain = 3.20 gain = 6.40 10516-139 figure 29 . cmrr vs . frequency
ADAS3022 data sheet rev. b | page 16 of 40 10516-301 ?50 ?55 ?60 ?65 ?70 ?75 ?80 ?85 ?90 ?95 ?100 0.01 100 10 1 0.1 power supply rejection ratio (db) frequency (khz) psrr vddh avdd, gain = 0.2 avdd, gain = 3.2 psrr vssh avdd, gain = 1.6 avdd, gain = 6.4 figure 30 . psrr vs. frequency 13 14 15 16 17 18 19 4.7 4.8 4.9 5.0 5.1 5.2 5.3 a vdd current (ma) a vdd supp l y (v) g a i n = 0 . 2 g a i n = 0 . 4 g a i n = 0 . 8 g a i n = 1 . 6 g a i n = 3 . 2 g a i n = 6 . 4 10516-130 figure 31 . avdd current vs. supply , internal reference 10 1 1 12 13 14 15 4.7 4.8 4.9 5.0 5.1 5.2 5.3 a vdd current (ma) a vdd supp l y (v) g a i n = 0 . 2 g a i n = 0 . 4 g a i n = 0 . 8 g a i n = 1 . 6 g a i n = 3 . 2 g a i n = 6 . 4 10516-131 figure 32 . avdd current vs. supply , external reference 10 12 14 16 18 20 10 100 1000 a vdd current (ma) throughput (ksps) g a i n = 0 . 2 g a i n = 0 . 4 g a i n = 0 . 8 g a i n = 1 . 6 g a i n = 3 . 2 g a i n = 6 . 4 10516-134 figure 33 . avdd current vs. throughput , internal reference 9 1 1 10 12 13 14 15 10 100 1000 a vdd current (ma) throughput (ksps) g a i n = 0 . 2 g a i n = 0 . 4 g a i n = 0 . 8 g a i n = 1 . 6 g a i n = 3 . 2 g a i n = 6 . 4 10516-135 figure 34 . avdd current vs. throughp ut, external reference 0.5 1.5 2.5 3.5 4.5 1.0 2.0 3.0 4.0 10 100 1000 dvdd current (ma) throughput (ksps) g a i n = 0 . 2 g a i n = 0 . 4 g a i n = 0 . 8 g a i n = 1 . 6 g a i n = 3 . 2 g a i n = 6 . 4 10516-136 figure 35 . dvdd current vs. throughput
data sheet ADAS3022 rev. b | page 17 of 40 0 3 6 9 12 15 18 10 100 1000 vddh current (ma) throughput (ksps) g a i n = 0 . 2 g a i n = 0 . 4 g a i n = 0 . 8 g a i n = 1 . 6 g a i n = 3 . 2 g a i n = 6 . 4 10516-137 figure 36 . vddh current vs. throughput ?18 ?15 ?12 ?9 ?6 ?3 0 10 100 1000 vssh current (ma) throughput (ksps) g a i n = 0 . 2 g a i n = 0 . 4 g a i n = 0 . 8 g a i n = 1 . 6 g a i n = 3 . 2 g a i n = 6 . 4 10516-138 figure 37 . vssh current vs. throughput 0 2 4 6 8 10 12 14 16 18 20 ?50 ?40 ?30 ?20 ?10 0 10 20 30 40 50 60 70 80 90 vddh current (ma) temper a ture (c) g a i n = 0 . 2 g a i n = 0 . 4 g a i n = 0 . 8 g a i n = 1 . 6 g a i n = 3 . 2 g a i n = 6 . 4 f s = 1000 ksps 10516-142 figure 38 . vddh current v s. temp erature ?20 ?18 ?16 ?14 ?12 ?10 ?8 ?6 ?4 ?2 0 ?50 ?40 ?30 ?20 ?10 0 10 20 30 40 50 60 70 80 90 vssh current (ma) temper a ture (c) g a i n = 0 . 2 g a i n = 0 . 4 g a i n = 0 . 8 g a i n = 1 . 6 g a i n = 3 . 2 g a i n = 6 . 4 f s = 1000 ksps 10516-143 figure 39 . vssh current v s. temp erature 16.0 16.5 17.0 17.5 18.0 18.5 19.0 19.5 ?50 ?40 ?30 ?20 ?10 0 10 20 30 40 50 60 70 80 90 a vdd current (ma) temper a ture (c) g a i n = 0 . 2 g a i n = 0 . 4 g a i n = 0 . 8 g a i n = 1 . 6 g a i n = 3 . 2 g a i n = 6 . 4 f s = 1000 ksps 10516-144 figure 40 . avdd current v s. temp erature 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 ?50 ?40 ?30 ?20 ?10 0 10 20 30 40 50 60 70 80 90 dvdd current (ma) temper a ture (c) g a i n = 0 . 2 g a i n = 0 . 4 g a i n = 0 . 8 g a i n = 1 . 6 g a i n = 3 . 2 g a i n = 6 . 4 f s = 1000 ksps vio = 3.3v 10516-146 figure 41 . dvdd current vs. temperature
ADAS3022 data sheet rev. b | page 18 of 40 2.00 2.25 2.50 2.75 3.00 3.25 3.50 3.75 4.00 ?50 ?40 ?30 ?20 ?10 0 10 20 30 40 50 60 70 80 90 vio current (ma) temper a ture (c) g a i n = 0 . 2 g a i n = 0 . 4 g a i n = 0 . 8 g a i n = 1 . 6 g a i n = 3 . 2 g a i n = 6 . 4 f s = 1000 ksps 10516-145 figur e 42 . vio current v s. temperature 80 82 84 86 88 90 92 94 96 98 100 ?50 ?40 ?30 ?20 ?10 0 10 20 30 40 50 60 70 80 90 snr (db) temper a ture (c) g a i n = 0 . 2 g a i n = 0 . 16 g a i n = 0 . 4 g a i n = 0 . 8 g a i n = 1 . 6 g a i n = 3 . 2 g a i n = 6 . 4 f s = 1000 ksps 10516-147 figure 43 . snr v s. temp erature ?120 ?1 15 ?1 10 ?105 ?100 ?95 ?90 ?85 ?80 ?50 ?40 ?30 ?20 ?10 0 10 20 30 40 50 60 70 80 90 thd (db) temper a ture (c) g a i n = 0 . 2 g a i n = 0 . 16 g a i n = 0 . 4 g a i n = 0 . 8 g a i n = 1 . 6 g a i n = 3 . 2 g a i n = 6 . 4 10516-148 figure 44 . thd v s. temp erature ?5 ?4 ?3 ?2 ?1 0 1 2 3 4 5 ?50 ?40 ?30 ?20 ?10 0 10 20 30 40 50 60 70 80 90 gain error (lsb) temper a ture (c) g a i n = 0 . 2 g a i n = 0 . 16 g a i n = 0 . 4 g a i n = 0 . 8 g a i n = 1 . 6 g a i n = 3 . 2 g a i n = 6 . 4 10516-149 f s = 1000 ksps externa l reference figure 45 . gain error v s. temperature ?12 ?8 ?4 0 4 8 12 ?50 ?40 ?30 ?20 ?10 0 10 20 30 40 50 60 70 80 90 offset error (lsb) temper a ture (c) g a i n = 0 . 2 g a i n = 0 . 16 g a i n = 0 . 4 g a i n = 0 . 8 g a i n = 1 . 6 g a i n = 3 . 2 g a i n = 6 . 4 f s = 1000 ksps externa l reference 10516-150 figure 46 . offset error v s. temperature ?5 ?4 ?3 ?2 ?1 0 1 2 3 4 5 ?50 ?40 ?30 ?20 ?10 0 10 20 30 40 50 60 70 80 90 error (lsb) temper a ture (c) f s = 1000 ksps externa l reference g a i n er r o r o ff s e t er r o r 10516-151 figure 47 . offset and gain errors of the aux adc channel pair vs. temperature
data sheet ADAS3022 rev. b | page 19 of 40 3400 3600 3800 4000 4200 4400 4600 4800 5000 5200 5400 5600 ?50 ?40 ?30 ?20 ?10 0 10 20 30 40 50 60 70 80 90 tem p sensor output code (lsb) temper a ture (c) 10516-152 figure 48 . temp erature sensor output code v s. temp erature ?4.5 ?4.0 ?3.5 ?3.0 ?2.5 ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 10 100 1k 10k normalized closed-loo p gain (db) frequenc y (hz) g a i n = 0 . 2 ?0.5dbfs g a i n = 0 . 4 g a i n = 0 . 8 g a i n = 1 . 6 g a i n = 3 . 2 g a i n = 6 . 4 10516-153 figure 49 . large signal frequency response v s. gain 0 4 8 12 16 20 24 28 32 0 5 10 15 20 25 0 100 200 300 400 500 600 700 800 900 1000 temperature sensor output error (c) temperature sensor output error (mv) throughput (ksps) t a = 25c internal reference 10516-154 figure 50 . temperature sensor output error v s. throughput
ADAS3022 data sheet rev. b | page 20 of 40 terminology operating input voltage range operating input voltage range is t he maximum input voltage range , including the common - mode voltage, allowed on the input channels in[7:0] and com. differential input voltage range differential input voltage range is t he maximum differential full - scale input range. the value changes according to th e programmable gain setting. channel off leakage channel off leakage is t he leakage current with the channel off. channel on leakage channel on leakage is t he leakage current with the channel on. charge injection charge injection is a measure of the glit ch impulse that is transferred through the analog input pin into the source when the sample is taken and/or the multiplexer is switched. common - mode rejection ratio (cmrr) cmrr is the ratio of the amplitude of a signal referred to input in the converted re sult t o the amplitude of the modulation common to a pair of inputs and is expressed in decibels . cmrr is a measure of the ability of the ADAS3022 to reject signals , such as power line noise, that are common to the inputs. this speci fication is for a 2 khz sine wave of 20.48 v p - p applied to both channels of an input pair. transient response transie nt r esponse is a measure of the time required for the ADAS3022 to properly acquire the input after a f ull - scale step function is applied to the system . least significan t bit (lsb) lsb is the smallest increment that can be represented by a converter. for a fully differential input adc with n bits of resolution, the lsb expressed in volts is n ref v lsb 2 2 (v) = integral nonlinearity (inl) error inl refers to the deviation of each individual code from a line drawn from negative full scale to positive full scale. the point used as negative full scale occurs ? lsb before the first code transition. positive full scale is defined as a level 1? lsb beyond the last code transition. the deviation is measured from the middle of each code to the true straight line (see figure 53). differential nonlinearity (dnl) error in an ideal adc, code transitions are 1 lsb apart. dnl is the maximum deviation from this ideal value. it is often specified in terms of resolution for which no missing codes are guaranteed. offset error offset error is the deviation of the actual msb transition from the ideal msb transition point. the ideal msb transition occurs at a n input level ? lsb above analog ground. gain error the last transition (from 111 10 to 111 11) for an analog voltage should occur 1? lsb below the nominal full scale. the gain error is t he deviation expressed in lsb (or as a percentage of the full - scale range) of the actual level of the last transition from the ideal level after the offset error is removed. closely related to this parameter is the full - scale error (also expressed in lsb o r as a percentage of the full - scale range), which includes the effects of the offset error. total unadjusted error (tue) tue is the deviation of each code from an ideal transfer function and is a combination of all error contributors , including non - linear ity , offset error , and gain error . tue for the ADAS3022 is expressed as the maximum deviation in l sb or as a percentage of the full - scale range. aperture delay aperture delay is a measure of the acquisition performance. it is the time between the rising edge of the cnv input and the point at which the input signal is held for a conversion. dynamic rang e dynamic range is the ratio of the rms value of the full - scale signal to the total rms noise measured with the inputs shorted together. the value for the dynamic range is expressed in decibels. signal -to - noise ratio (snr) snr is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the nyquist frequency, excluding harmonics and dc. the value for snr is expressed in decibels. signa l-to - noise - and - distortion ratio (sinad) sinad is the ratio of the rms valu e of the actual input signal to the rms sum of all other spectral components below the nyquist frequency, including harmonics but excluding dc. the value for sinad is expressed in decibels.
data sheet ADAS3022 rev. b | page 21 of 40 total harmonic distortion (thd) thd is the ratio of the rms sum of the first five harmonic components to the rms value of a full - scale input signal and is expressed in decibels. spurious - free dynamic range (sfdr) sfdr is the difference, expressed in decibels, between the rms amplitude of the input signal and the peak spu rious signal. channel -to - channel crosstalk channel - to - channel crosstalk is a measure of the level of crosstalk between any channel and all other channels . the crosstalk is measured by applying a dc input to the channel under test and applying a full - scale, 10 khz sine wave signal to all other channel s. the crosstalk is the amount of signal that leaks into the test channel and is expressed in decibels. reference voltage temperature coefficient reference voltage temperature coefficient is derived from the typ ical shift of output voltage at 25c on a sample of parts at the maximum and minimum reference output voltage (v ref ) measured at t min , t (25c), and t max . the value is expressed in ppm/c as 6 10 ) C ( ) ( ) ( C ) ( ) c ppm/ ( = min max ref ref ref ref t t c 25 v min v max v tcv where: v ref (max) is the maximum referenc e output voltage at t min , t (25c), or t max . v ref ( min ) is the minimum reference output voltage at t min , t (25c), or t max . v ref (25 c ) is the reference output voltage at 25c. t max = +8 5c. t min = ? 4 0c.
ADAS3022 data sheet rev. b | page 22 of 40 theory of operation overview the ADAS3022 is the first system on a single chip that integrat es the typical components used in a data acquisition system in one easy to use , programmable device . this single - chip solution is capable of converting up to 1,00 0 ,000 samples per second ( 1 m sps ) of aggregate throughput . t he ADAS3022 features ? high impedance inputs ? high common - mode rejection ? 8 - channel, low crosstalk multiplexer (mux) ? p rogrammable gain instrumentation amplifier (pgia) with seven selectable differential input ranges from 0 .64 v to 24. 576 v ? 16- bit pulsar ? adc with no missing codes ? internal, precision, low drift 4.096 v reference and buffer ? temperature sensor ? channel sequencer the ADAS3022 uses a n analog devices patented high voltage i cmos ? process , allowing up to a 24.576 v differential input voltage range when using 15 v supplies, w hich makes the device suitable for industrial applications . the device is housed in a small , 6 mm 6 mm, 40- lead lfcsp and can operat e over the industrial temperature range ( ? 4 0 c to + 8 5 c) . a typical discrete multi channel data acquisition system containing similar circuitry would require at least three times more space on the circuit board . therefore , advantages of the ADAS3022 solutio n include reduced footprint and less complex design requirements , which also results in faste r time to market and lower cost . ADAS3022 operation as shown in figure 51, t he ADAS3022 internal analog circuitry consists of a high impedance , low leakage multiplexer and a programmable gain instrumentation amplifier that can accept full - scale differential voltages of 0.64 v, 1.2 8 v , 2.56 v, 5.12 v, 1 0 .24 v , 20.48 v , and 24.576 v . the ADAS3022 can be con - figured to use up to eight single - ended input channels or four pairs of channels , that is, 12 5 ksps per channel for eight channels or effectively 250 ksps for four channel pairs . the device can also provide a relative temperature measurement using the internal temperature sensor. in addition , the differential auxiliary channel pair (aux+ and aux?) is provided with the specified input range of v ref . this option bypasses the mux and pgia stage s, allowing direct access to the sar adc core. reducing the number of channels or pairs increases the throughput rate by an amount proportional to the recipro cal of the number of sampled channels multiplied by the aggregate throughput : 1/( number of channels or pairs ) 1000 ksps for a single channel or channel pair , the max imum throughp ut rate is 1 m sps. fo r all eight chann els, the aux channel pair, and the te mperature sensor, the throughput rate of a given channel decreases to 100 ksps. in4 in5 in3 in2 buf in6 in7 in1 in0 in0/in1 pair diff to diff com in2/in3 in4/in5 in6/in7 pulsar adc logic/ interface refin ref refx cnv reset pd sck din sdo vssh vddh agnd vio dvdd avdd dgnd cs com aux+ aux? busy ADAS3022 mux temp sensor 10516-005 pgia figure 51 . ADAS3022 simplified block diagram
data sheet ADAS3022 rev. b | page 23 of 40 the ADAS3022 offers true high impedance inputs in a differential structure and rejects common - mode signals present on the inputs. th e adas302 2 architecture does not require any of the additional input buffers (op amps) that are usually required to condition the input signal and drive the adc inputs when using switched capacitor - based successive approximation register (sar) analog - to - digital converters (adcs). the inputs are multiplexed to the pgia using a high voltage multiplexer with low charge injection and very low leakage. the inputs can be configured for a single - ended to common point (com) measurement or can be paired for up to four ful ly differential inputs with independent gain settings. this requires using the advanced sequencer or program ming sequential configuration words with the desired gain for each pair. the digitally controlled, program mable gain is used to select one of seven voltage input ranges (see table 7 ). when the sequencer option is used, an on - chip sequencer scans channels in order and offers independent input voltage ranges for each channel (see the channel sequencer details section). in this mode, a single configuration word initiates the sequencer to scan repeatedly without the need to rewrite the register. after the last channel is scanned, the ADAS3022 automatically begins at in0 again and repeats the sequence until a word is written to stop the sequencer or the asynchronous reset is asserted. additionally, i f changes are made to certain configuration bits, the sequencer is reset to in0. the pulsar - based adc core is capable of converting 1 m sps from a single rising edge o n the convert start input (cnv). the conversion results are available in two s complement format and are presented on the serial data output (sdo). the digital interface uses a dedicated chip select pin ( cs ) to transfer data to and from the ADAS3022 and also provides a busy indicator , asynchronous reset , and power - down (pd) inputs. the ADAS3022 on - c hip referenc e uses an internal temperature compensated 2.5 v output band gap reference a nd a precision buffer amplifier to provide the 4.096 v high precision system reference. all of the bits in table 11 are configured through a serial ( spi - compatible ) , 16- bit configuration register ( cfg ) . configuration and c onversion results can be read after or during a conversion , or the read back option can be disabled. the ADAS3022 requires a minimum of three power supplies : + 5 v, + 15 v , and ? 15 v . o n - chip low drop out regulator s provide the necessary 2.5 v system voltages and must be decoupled externally vi a dedicated pins ( a cap , dcap, and rcap ) . the ADAS3022 can be interfaced to any 1.8 v to 5 v digital logic family using the dedicated vio logic level voltage supply (s ee table 9 ) . a rising edge on cnv initiates a conversion and changes the state of the ADAS3022 from track to hold. in this state, the ADAS3022 performs analog signal conditioning. when the signal conditioning is complete , the ADAS3022 returns to the track state while at the same time quantizing the sample . th is two - part process satisf ies the necessary settling time requirement while achieving a fast throughput rate of up to 1 m sps with 16 - bit accuracy. phase cnv hold convert/track t cyc t acq 10516-006 figure 52 . ADAS3022 system timing regardless of the type of signal ( differential or single - e nded, antiphase or nonanti phase, symmetric or asymmetric ), the ADAS3022 converts all signals present on the enabled inputs in a differential fashi on , like an industr y - standard difference or instrumentation amplifier. the conversion result is available after the conversion is complete and can be read back at any time before the end of the next conversion. reading back data should be avoided during th e quiet period , as indicated by busy being active high. because the ADAS3022 has an on - board conversion clock, the serial clock ( sck ) is not requi red for the conversion process. it is only required to present results to the user. transfer function the ideal transfer characteristic s of the adas 3022 are shown in figure 53. with the inputs configured for differential input range s , the data output is twos complement , as described in table 6 . 100 ... 000 100 ... 001 100 ... 010 011 ... 101 011 ... 110 011 ... 111 twos complement adc code analog input +fsr ? 1.5lsb +fsr ? 1lsb ?fsr + 1lsb ?fsr ?fsr + 0.5lsb 10516-007 figure 53 . adc ideal t ransfer function
ADAS3022 data sheet rev. b | page 24 of 40 table 6 . output codes and ideal input voltages description differential analog inputs, v ref = 4.096 v digital output code (twos complement , hex) fsr ? 1 lsb (32,767 v ref )/ (32,768 pgia gain) 0x7fff midscale + 1 lsb v ref /(32,768 pgia gain) 0x0001 midscale 0 0x0000 midscale ? 1 lsb ?(v ref /(32,768 pgia gain)) 0xffff ?fsr + 1 lsb ?(32,767 v ref )/ (32,768 pgia gain) 0x8001 ?fsr ?v ref pgia gain 0x8000 typical application connection diagram as shown in figure 54 , the adp1613 is used in an inexpensive sepic - ? uk topology, which is an ideal candidate for providing the ADAS3022 with the necessary high voltage 15 v robust supplies (at 20 ma) and low output ripple (3 mv maximum) from an external 5 v supply. the adp1613 satisfies the specification requirements of the ADAS3022 with minim al external comp onents while achiev ing greater than 86% of efficiency. refer to the cn - 0201 circuit note for complete information about this test setup. in0 in0/in1 in2/in3 in4/in5 in6/in7 in1 in2 in3 in4 in5 in6 in7 diff pair diff com logic/ interface refin ref mux cnv reset sck din sdo vddh avdd dvdd vio cs com aux+ aux? busy + + + enable adp1613 ADAS3022 comp fb freq en vin gnd ss sw + + v in = +5v + + + + vssh rf2 4.22k? rf1b 47.5k? r c 1 100k? c c 1 12nf c c 2 10pf c v 5 1f r en r b 0 1? r s 1 0? r s 2 dni c ss 1f z 1 c in 1f d1 d 2 c1 1f c2 1f l3 1f c out 3 4.7f c out 1 1f c out 2 2.2f +15v ?15v +5v adr434 refx pd agnd dgnd ad8031 4.096v + ? 1.78? r filt dni 50k? l1 47h l2 47h + +5v +5v buf pulsar adc 10516-200 temp sensor pgia figure 54 . complete 5 v, single - supply, 8 - channel multiplexed data acquisition system with pg i a
data sheet ADAS3022 rev. b | page 25 of 40 analog inputs input structure the ADAS3022 uses a differential input structure between in[7:0] and com or between in[7:0]+ and in[7:0]? of a channel pair. the com input is sampled identically such that the same voltages can be present on inputs in[7:0]. therefore, the selection of paired channels or all channels referenced to one common point is available. because all inputs are sampled differentially, the ADAS3022 offers true high common-mode rejection, whereas a discrete system would require the use of additional instrumentation or a difference amplifier. figure 55 shows an equivalent circuit of the analog inputs. the internal diodes provide esd protection for the analog inputs (in[7:0] and com) from the high voltage supplies (vddh and vssh). care must be taken to ensure that the analog input signal does not exceed the supply rails by more than 0.3 v because this can cause the diodes to become forward-biased and to start conducting current. note that if the auxiliary input pair (aux) is used, the diodes provide esd protection from only the lower voltage avdd (5 v) supply and the system analog ground because these inputs are connected directly to the internal sar adc circuitry. c pin c pin in[7:0] or com vssh aux+ o r aux? agnd v ddh avdd mux pgia 10516-008 figure 55. equivalent analog input circuit voltages beyond the absolute maximum ratings may cause permanent damage to the ADAS3022 (see table 4). programmable gain the ADAS3022 incorporates a programmable gain instru- mentation amplifier with seven selectable ranges (0.64 v, 1.28 v, 2.56 v, 5.12 v, 10.24 v, 20.48 v, and 24.576 v), enabling the use of almost any direct sensor interface. the pgia settings are specified in terms of the maximum absolute differential input voltage across a pair of inputs (for example, inx+ to inx? or inx+ to com). the power-on and default conditions are preset to the 20.48 v (pgia = 111) input range. note that because the ADAS3022 can use any input type, such as bipolar differential (antiphase or nonantiphase), bipolar single ended, or pseudo bipolar, setting the pgia is important to make full use of the allowable input span. table 7 describes each differential input range and the corresponding lsb size, pgia bits settings, and pgia gain. table 7. differential input ranges, lsb size, and pgia settings differential input ranges, inx+ ? inx ? (v) lsb (v) pgia bits pgia gain (v/v) 24.576 781.25 000 0.16 20.48 625 111 0.2 10.24 312.5 001 0.4 5.12 156.3 010 0.8 2.56 78.13 011 1.6 1.28 39.06 100 3.2 0.64 19.53 101 6.4 common-mode operating range the differential input common-mode voltage (v cm ) range changes according to the maximum input range selected and the high voltage power supplies (vddh and vssh). note that the specified operating input voltage of any input pin (see the specifications section) requires 2.5 v of headroom from the vddh and vssh supplies; therefore, ( vssh + 2.5 v) inx / com ( vddh ? 2.5 v) this section provides some examples of setting the pgia for various input signals. note that the ADAS3022 always calculates the difference between the in+ and in? signals. fully differential, antiphase signals with a zero common mode for a pair of 20.48 v p-p differential antiphase signals with a zero common mode, the maximum differential voltage across the inputs is ? 20.48 v, and the pgia gain configuration should be set to 111. ADAS3022 inx+ inx+ +10.24 v 20.48v p-p 20.48v p-p ? 10.24 v inx? inx? 10516-009 figure 56. differential, antiphase inputs with a zero common mode
ADAS3022 data sheet rev. b | page 26 of 40 fully differential, antiphase signals with a nonzero common mode for a pair of 5.12 v p-p differential antiphase signals with a nonzero common mode (dc common-mode voltage of 7 v in this example), the maximum differential voltage across the inputs is ? 5.12 v (dc common-mode voltage is rejected), and the pgia gain configuration should be set to 010. ADAS3022 inx + inx+ 0v 5.12v p-p 5.12v p-p inx? inx? v cm = 7v v cm 10516-010 figure 57. differential, antiphase inputs with a nonzero common mode differential, nonantiphase signals with a zero common mode for a pair of 10.24 v p-p differential nonantiphase signals with a zero common mode, the maximum differential voltage across the inputs is ? 10.24 v, and the pgia gain configuration should be set to 001. ADAS3022 inx+ +5.12v 10.24v p-p 0v inx? ?5.12v 10.24v p-p 10516-011 inx + inx? figure 58. differential, nonantiphase inputs with a zero common mode single-ended signals with a nonzero dc offset (asymmetrical) when a 12 v p-p signal with a 6 v dc level-shift is connected to one input (inx+) and the dc ground sense of the signal is connected to inx? or com, the pgia gain configuration is set to 000 for the 24.576 v range because the maximum differential voltage across the inputs is 12 v p-p and only half the codes available for the transfer function are used. ADAS3022 inx+ inx+ +12v 12v p-p 0v v off v off inx? inx? 10516-012 figure 59. typical single-ended unipolar inputuses only half the codes single-ended signals with a 0 v dc offset (symmetrical) compared with the example in the single-ended signals with a nonzero dc offset (asymmetrical) section, a better solution for single-ended signals, if possible, is to remove as much dc offset as possible between inx+ and inx? to produce a bipolar input voltage that is symmetric around the ground sense. in this example, the differential voltage across the inputs is never greater than 0.64 v, and the pgia gain configuration is set to 101 for the 1.28 v p-p range. this scenario uses all of the codes available for the transfer function, making full use of the allowable differential input range. ADAS3022 inx + inx+ +0.64v 1.28v p-p ?0.64v inx? inx? 10516-013 figure 60. better single-ended configurationuses all codes notice that the voltages in this example are not integer values due to the 4.096 v reference and the pgia scaling ratios. multiplexer the ADAS3022 uses a high voltage, high performance, low charge injection multiplexer and a total of nine inputs (in[7:0] and com). using the inx and com bits of the configuration register, the ADAS3022 is configurable for differential inputs between any of the eight input channels (in[7:0]) and com or for up to four input pairs. figure 61 shows various methods for configuring the analog inputs for the type of channel (single or paired). refer to the configuration register section for more information. the analog inputs can be configured as follows: ? figure 61a: in[7:0] referenced to a system ground. ? figure 61b: in[7:0] with a common reference point. ? figure 61c: in[7:0] differential pairs. for pairs, com = 0. the positive channel is configured with inx. if inx is even, then in0, in2, in4, and in6 are used. if inx is odd, then in1, in3, in5, and in7 are used, as indicated by the channels with parentheses in figure 61c. for example, for the in0/in1 pair with the positive channel on in0, inx = 000 2 . for the in4/in5 pair with the positive channel on in5, inx = 101 2 . note that when the channel sequencer is used, as detailed in the channel sequencer details section, the positive channels are always in0, in2, in4, and in6. ? figure 61d: inputs configured in a combination of any of the preceding configurations (showing that the ADAS3022 can be configured dynamically).
data sheet ADAS3022 rev. b | page 27 of 40 in0+ com? in0 in1+ in2+ in3+ in4+ in5+ in6+ in7+ in0+ in1+ in2+ in3+ in4+ in5+ in6+ in7+ in1 in2 in3 in4 in5 in6 in7 com in0 in1 in2 in3 in4 in5 in6 in7 com a?8 channels, single-ended b?8 channels, common reference 10516-014 in2+ in3+ in4+ in5+ in0 in1 in2 in3 in4 in5 in6 in7 com in0 in1 in2 in3 in4 in5 in6 in7 com in0+ (?) c?4 channels, differential d?combination com? in0? (+) in1+ (?) in1? (+) in0+ (?) in0? (+) in1+ (?) in1? (+) in2+ (?) in2? (+) in3+ (?) in3? (+) figure 61 . multiplexed analog input configurations channel sequencer the ADAS3022 includes a channel sequencer that is useful for scanning cha nnels in a repeated fashion. refer to the channel sequencer details section for more information . auxiliary input channel the ADAS3022 includes an auxiliary input channel pair (aux+ and aux?) that bypasses the mux and pgia stage s , allowing direct access to the sar adc core for applications where the additional dedicated channel pair is required . as deta iled previously, the inputs are protected only from avdd and agnd because the high voltage supplies are used for the mux and pgia stages but not the lower voltage adc core. when the source impedance of the driving circuit is low, the aux inputs can be dri ven directly. large source impedances significantly affect the ac performance, especially thd. the dc performance parameters are less sensitive to the input impedance. the maximum source impedance depends on the amount of thd that can be tolerated. the thd degrades as a function of the source impedance and the maximum input frequency. driver amplifier choice for systems that cannot drive aux directly, a suitable op amp buffer should be used to preserve the ADAS3022 performance. the driver amplifier must meet the following requirements: ? the noise generated by the driver amplifier must be kept as low as possible to preserve the snr and the transition noise performance of the ADAS3022 . the noise from the amplifier is filtered by the ADAS3022 analog input circuit or by an external filter, if one is used. because the typical noise of the ADAS3022 s sar adc core is 35 v rms (v ref = 4.096 v) , the snr degradation due to the amplifier is ? ? ? ? ? ? ? ? ? ? ? ? + = ? 2 2 ) ( 2 35 35 log 20 n 3db loss ne f snr where: f ? 3db is the input bandwidth ( 8 mhz ) of the ADAS3022 s sa r adc core expressed in megahertz or the cutoff frequency of an input filter, if one is used. n is the noise gain of the amplifier (for example, 1 in buffer c onfiguration). e n is the equivalent input noise voltage of the op amp expressed in nv/hz. ? for ac applications, the driver should have a thd performance commensurate with the ADAS3022 . ? the analog input circuit must settle a fu ll- scale step onto the capacitor array at a 16 - bit level (0.0015%). in amplifier data sheets, settling at 0.1% to 0.01% is more commonly specified. this may differ significantly from the settling time at a 16 - bit level and should be verified prior to drive r selection. table 8 . recommended driver amplifiers amplifier typical application ada4841 - 1 , ada4841 - 2 very low noise, small, and low power ada4897 - 1 , ada4897 - 2 very low noise, low and high frequenc ies ad8655 5 v single supply, low noise ad8021 , ad80 22 very low noise and high frequency op184 low power, low noise, and low frequency ad8605 , ad86 15 5 v single supply, low power
ADAS3022 data sheet rev. b | page 28 of 40 vo ltage reference output/ input the ADAS3022 allows the choice of an internal reference or an external reference using the on - chip buffer/amplifier, or an external reference . the internal reference of the ADAS3022 provides excellent performance and can be used in almost all applications. to s et the referenc e selection mod e , use the internal reference enable bit ( refen ) and the refin pin as described in this section . ref1 and ref2 must be tied together externally. internal reference the precision internal reference is factory trimmed and is suitable for most applications. setting the refen bit in the cfg register to 1 (default) enables the internal reference and produces 4.096 v on the ref1 and ref2 pins ; this 4.096 v output serves as th e main system reference. the un buffered 2.5 v (typical) band gap voltage is output on the refin pin, which requires an external parallel decoupling using 10 f and 0.1 f capacitors to reduce the noise on the output. because the current output of refin is limited, it can be used as a source if followed by a suitable buffer, suc h as the ad8031 . note that excessive loading of the refin output will also lower the 4.096 v system reference because the internal amplifier uses a fixed gain. the internal reference output is tr immed to the targeted value of 4.096 v with an initial accuracy of 8 mv . the reference is also temperature compensated to provide a typical drift of 5 ppm/c. when the internal reference is used , the ADAS3022 should be decoupled as shown in figure 62 . note that both ref1 and ref2 connections are required , along with suitab le decoupling on the refin output and the rcap internally regulated supply. r e f 2 r e f 1 rc a p r e f n rgnd band gap ADAS3022 0 . 1 f r e f i n r e f n 1 0 f 1 0 f 0 . 1 f 1 0 f 0 . 1 f 1 f r e f n 10516-016 figure 62 . 4.096 v internal reference connection external reference and internal buffer th e external reference and internal buffer are useful whe n a com - mon system reference is used or if improved drift performance is required. setting refen to 0 disables the internal band gap reference , allowing the user to provide an external voltage referen ce (2.5 v typical ) to the refin pin. the internal buffer remain s enabled, thus reducing the need for an external buffer amplifier to gener ate the main system reference. with refin = 2.5 v, ref1 an d ref2 output 4.096 v, which serves as the main system reference. for this configuration, connect the external source as sh own in figure 63 . any type of 2.5 v reference , including those with low power, low drift, and a small package, ca n be used in this configuration because the internal buffer handles the dynamics of the ADAS3022 reference. ref2 ref1 rcap refn r g n d band gap ADAS3022 0 . 1 f refin refn 1 0 f 1 0 f 0 . 1 f 1 0 f 0 . 1 f 1 f refn reference source = 2.5v 10516-017 figure 63 . external reference using internal buffer external reference for a pplications that require a precise, low drift 4.096 v reference, an external reference can also be used. this option requires disabling the internal buffer by setting refen to 0 and driving or connecting refin to agnd; therefore, both hardware and software control are necessary. attempting to drive the ref1 and ref2 pins prior to disabling the internal buffer can cause source/sink contention in the driving amplifiers . c onnect the precision 4.096 v reference , which serves as the main system reference, throu gh a low impedance buffer (such as the ad8031 or the ad8605 ) to ref1 and ref2 as shown in figure 64 . recommended references in clude the adr434 , adr444 , and adr4540 . ref2 ref1 rcap refn rgnd band gap ADAS3022 0 . 1 f refin refn 1 0 f 1 0 f 0 . 1 f 1f reference source = 4.096v 10516-018 figure 64 . external reference if an op amp is used as the external reference source, take note of any concerns regarding driving capacitive loads. capacitive loading for op amps usually refers to the ability of the amplifier to remain marginally stable in ac applicat ions but can also play a role in dc applications, such as a reference source. keep in mind that the reference source see s the dynamics of the bit decision process on the reference pins and further analysis beyond the scope of this data sheet may be require d.
data sheet ADAS3022 rev. b | page 29 of 40 reference decoupling with any of the reference topologies described in the voltage reference input/output section, the ref1 and ref2 reference pins of the ADAS3022 have dynamic impedances and require sufficient decoupling, regardless of whether the pins are used as inputs or outputs. this decoupling usually consists of a low esr capacitor connected to each ref1 and ref2 and to the accom- panying refn return paths. using x5r, 1206 size ceramic chip capacitors is recommended for decoupling in all the reference topologies described in the voltage reference input/output section. the placement of the reference decoupling capacitors plays an important role in the system performance. mount the decoupling capacitors on the same side as the ADAS3022 , close to the ref1 and ref2 pins, with thick pcb traces. route the return paths to the refn inputs, which are in turn connected to the analog ground plane of the system. the resistance of the return path to ground should be minimized by using as many through vias as possible when it is necessary to connect to an internal pcb layer. the refn and rgnd inputs should be connected with the shortest distance to the analog ground plane of the system, preferably adjacent to the solder pads, using several vias. one common mistake is to route these traces to an individual trace that connects to the ground of the system. this can introduce noise, which may adversely affect lsb sensitivity. to prevent such noise, it is highly recommended to use pcbs with multiple layers, including ground planes, rather than using single- or double-sided boards. refer to ug-484 for more information about the pcb layout of the eval-ADAS3022edz . for applications that use multiple ADAS3022 devices or other pulsar adcs, it is more effective to use the internal reference buffer to buffer the external reference voltage, thus reducing sar conversion crosstalk. the voltage reference temperature coefficient (tc) directly affects the full-scale accuracy of the system; therefore, in applications where full-scale accuracy is crucial, care must be taken with the tc. for example, a 15 ppm/c tc of the reference changes the full-scale accuracy by 1 lsb/c. power supply the ADAS3022 uses five supplies: avdd, dvdd, vio, vddh, and vssh (see table 9). note that acap, dcap, and rcap are included in table 9 for informational purposes only because these supplies are outputs of the on-chip supply regulators. refer to ug-484 for more information about how these supplies are generated on the eval-ADAS3022edz . table 9. power supplies name function required avdd analog 5 v core yes dvdd digital 5 v core yes, or can connect to avdd vio digital input/output yes, and can connect to dvdd (for 5 v level) vddh positive high voltage yes, +15 v typ vssh negative high voltage yes, ?15 v typ acap analog 2.5 v core no, on chip dcap digital 2.5 v core no, on chip rcap analog 2.5 v core no, on chip core supplies avdd and dvdd supply the ADAS3022 analog and digital cores, respectively. sufficient decoupling of these supplies is required, consisting of at least a 10 f capacitor and a 100 nf capacitor on each supply. the 100 nf capacitors should be placed as close as possible to the ADAS3022 . to reduce the number of supplies needed, dvdd can be supplied from the analog supply by connecting a simple rc filter between avdd and dvdd, as shown in figure 65. vio is the variable digital input/output supply and can be directly interfaced to any logic between 1.8 v and 5 v (dvdd supply maximum). to reduce the supplies needed, vio can alternatively be connected to dvdd when dvdd is supplied from the analog supply through an rc filter. the recommended low dropout regulators are adp3334 , adp1715 , and adp7102 / adp7104 for the avdd, dvdd, and vio supplies. avdd 10f 100nf 100nf agnd dgnd dgnd dvdd ADAS3022 vio 1.8v to 5v digital i/o supply analog supply +5v +5v digital supply 10f 10f 20 ? vddh vssh 10f 100nf +15 v ? 15 v 10f 100nf 100nf 10516-020 figure 65. ADAS3022 supply connections
ADAS3022 data sheet rev. b | page 30 of 40 high voltage supplies the high voltage bipolar supplies ( vddh and vssh ) are required and must be at least 2.5 v larger than the maximum input. for exa mple, the supplies should be 15 v for headroom in the 24.576 v differential input range. sufficient decoupling of these supplies is also required , consisting of at least a 10 f capacitor and a 100 nf capacitor on each supply. pow er dissipation mode s the ADAS3022 offers two power dissipation modes : fully operational mode and power - down mode . fully operational mode in fully operational mode, the ADAS3022 can perform conversions as soon as all internal bias currents are established. power - down mode to minimize the operating current s of the device when it is idle , place the device in full p ower - down mode by bringing the pd input high. t his places the ADAS3022 into a deep sleep mode , in which cnv activity is ignored and the digital interface is inactive. refer to the reset and power - down (pd) inputs section for timing details. in deep sleep mode, the internal regulators ( acap, rcap , and dcap ) and the voltage ref erence are also powered down. to reestablish operation, return pd low. note that before the device can operate at the specified performance, the reference voltage must charge up the external reservoir capacitor(s) and be allowed the specified settling ti me . returning pd low also resets the ADAS3022 digital core, including the cfg register , to it s def ault state. th erefore , the desired cfg must be rewritten to the device and two dummy conversions must be completed before the device operation is restored to the configuration programmed prior to pd a ssertion. conversion modes the ADAS3022 offers two conversion modes to accommodate varying applications . t he mode is set with the conversion mode select b it ( cms , bit 1 of the cfg register) . warp mode (cms = 0) setting cms to 0 is useful whe n an aggregate throughput rate of 1 msps is required. however, in this mode , the maximum time between conversions is restricted. if this maximum period is exceeded, the conversion result may be corrupt ed . therefore, t his mode is more suit able for continually sampled applications. normal mode (cms = 1, default) setting cms to 1 is useful for all applications with a maximum aggregate throughput of 900 ksps. in this mode, t here is no restriction in terms of the maximum time between conversions. this mode is the default condition from the assertion of an asynchronous reset. the main difference between normal mode and warp mode is the busy time; t quiet is slightly longer in no rmal mode than it is in warp mode.
data sheet ADAS3022 rev. b | page 31 of 40 digital interface the ADAS3022 digital interface consists of a synchronous inputs, a busy indicator , and a 4 - wire serial interface for conversion result readback and configuration register programming. this interface uses the three asynchronous signals ( c n v, reset, and pd ) and a 4 - wire serial interface comp o sed of cs , sdo, sck, and din. cs can also be tied to cnv for some applications. conversion results are available on the serial data output pin ( sdo ), and t he 16 - bit configuration word ( cfg ) is program - med on the serial d ata input pin ( din ) . this register controls settings such as the channel to be converted, the programmable gain setting, and the reference choice (see the configuration register section for more information) . conversion control c onversions are initiated by the cnv input. the ADAS3022 is fully asynchronous and can perform conv ersions at any frequency from dc up to 1 m hz , depending on the conversion mode . cnv rising edge start of a conversion (soc) a rising edge on cnv changes the state of the ADAS3022 from track mode to hold mode and is all that is necessary to initiate a conversion . a ll conversion timing clocks are internal ly generated . after a conversion is initiated, the ADAS3022 ignores other activity on the cnv line (governed by the throughput rate ) until the end o f the conversion ; the conversion can only be aborted by the power - down (pd) or reset inputs. wh en the ADAS3022 is performing a conversion and the busy output is driven high, the ADAS3022 uses a un ique 2 - phase conversion process to allow for safe data access and quiet time s. the cnv signal is decoupled from the cs pin, allowing multiple ADAS3022 device s to be controlled by the same processor. for applications where snr is critical, the cnv source should have very low jitter. this can be achieved by using a dedicated oscill ator or by clocking cnv with a high frequency, low jitter clock. for applications where jitter is more tolerable or a single device is in use , cnv can be tied to cs . for more information about sample clock jitter and aperture delay, refer to the mt - 007 tutor ia l , aperture time, aperture jitter, aperture delay time removing the confusion . although cnv is a digital signal, it should be designed to ensure fast, clean edges with minim al overshoot , undershoot, and ringing. the cnv trace should be shielded by connect ing a trace to ground , and a low value (such as 50 ?) serial resistor termination should be added close to the output of the component that drives this line. in addition, care should be taken to avoid digital activity close to the sampling instant because such activity may resu lt in degraded snr performance. busy falling edge end of a conversion (eoc) the eoc event is indicated by busy returning low and can be used as a host interrupt. in addition, the eoc gates data access to and from the ADAS3022 . if the current conversion result is not read prior to the following eoc event, the data is lost. furthermore, if the cfg update is not completed prior to eoc, it is discarded and the current configuration is appl ied to future con - versions. this pipeline ensures that the ADAS3022 has sufficient time to acquire the next sample to the specified 16 - bit accuracy. conversion timing a detailed timing diagram of the conversion process is shown in figure 66. conver- sion acqui- sition cnv cs sdo din busy (n) safe xxx xxx quiet data (n ? 1) cfg (n + 2) x x cfg (n + 3) data (n) x (n + 1) (n + 1) (n) eoc (n) soc (n) t ddc t ch t cyc t quiet t dac t ad t acq t ccs t cbd t conv t cc s t ddca soc (n + 1) 10516-022 figure 66 . basic conversion timing register pipeline to ensure that all cfg updates are applied during a known safe instant to the various circuit elements, the asynchronous data transfer is synchronized to the ADAS3022 timi ng engine using the eoc event. this synchronization introduces an inherent delay between updating the cfg register setting and the application of the configuration to a conversion. this pipeline from the end of the current conversion (n) consists of a two - deep delay (shown as (n + 2) in figure 66 ) before the cfg setting takes eff ect . this means that two soc and eoc events must e lapse before the setting (that is, new channel , gain , and so on ) take s effect. note that the nomenclature (n), (n + 1), and so on is used in the remainder of the following digital sections for simplicity. t here is no pipeline after the end of a conversion , however, before data can be read back.
ADAS3022 data sheet rev. b | page 32 of 40 reset and power-down (pd) inputs the asynchronous reset and pd inputs can be used to reset and power down the ADAS3022 , respectively. timing details are shown in figure 67. a rising edge on reset or pd aborts the conversion process and places sdo into high impedance, regardless of the cs level. note that reset has a minimum pulse width (active high) time for setting the ADAS3022 into the reset state. see the configuration register section for the default cfg setting when the ADAS3022 returns from the reset state. if the default setting is used after reset is deasserted (logic 0), a period equal to the acquisition time (t acq ) must elapse before cnv can be asserted for the conversion result to be valid. if a conversion is initiated, the result will be corrupted. in addition, the output data from the previous conversion is cleared upon a reset. attempting to access the data result prior to initiating a new conversion results in an invalid result. when the device returns from power-down mode or from a reset and the default cfg is not used, there is no t acq requirement; the first two conversions from power-up are undefined/invalid because the two-deep delay pipeline requirement must be satisfied to reconfigure the device to the desired setting. cs sdo cnv n?1 n?1 n see note see note n?1 n?2 xx x busy reset/ pd t acq t dis t en t rh cfg n+1 x n+2 notes 1. when the part is released from reset, t acq must be met for conversion n if using the default cfg setting for channel in0. when the part is released from power-down, t acq is not required, and the first two conversions, n and n + 1, are undefined. 10516-023 figure 67. reset and pd timing serial data interface the ADAS3022 uses a simple 4-wire interface and is compatible with fpgas, dsps, and common serial interfaces, such as spi, qspi, and microwire?. the interface uses the cs , sck, sdo, and din signals. timing details for the serial interface are shown in figure 68. sdo is activated when cs is asserted. the conversion result is output on sdo and is updated on sck falling edges. simultaneously, the 16-bit cfg word is updated, if desired, on the serial data input (din). the state of the clock phase select bit (cpha, bit 0) determines whether the msb is output again on the first clock or whether the msb ? 1 bit is output when sdo is activated after the eoc. note that in figure 67 and figure 68, sck is shown idling high. sck can idle high or low, requiring that the system developer design an interface that suits setup and hold times for both sdo and din. din (mosi) sdo (miso) cs sck t en t sdod t sdoh t sck t dis t dinh t dins t sckh t sckl 10516-024 figure 68. serial timing cpha the clock phase select bit (cpha, bit 0) sets the first bit of the conversion result on sdo after the end of a conversion (see figure 69). setting cpha to 0 outputs the msb when cs is asserted. sub- sequent sck falling edges clock out bits in an msb ? 1, msb ? 2, and so on fashion. this mode is useful for hosts limited to 16 clock edges where the first falling (or rising) edge can be used to latch the data. setting cpha to 1 outputs the msb not only when cs is asserted but also after the first sck falling edge. subsequent sck falling edges clock out bits in an msb ? 1, msb ? 2, and so on fashion. this mode can be useful for sign extension applications. sdo cpha = 1 sdo cpha = 0 cs sck msb msb lsb lsb + 1 msb ? 1 msb ? 2 msb 1 216 15 lsb + 1 lsb lsb + 2 msb msb ? 1 10516-025 figure 69. cpha details sampling on the sck falling edge to achieve the fastest data transfer rate, the host should sample data on the sck falling edge, as long as there is a sufficient hold time of t sdoh (see figure 68). when using this method, data transfers should occur during the safe conversion time (t ddc ). because this time is fixed, extending data reading or writing into the quiet conversion phase (t quiet ) may cause data corruption. however, for systems that need slightly more time, t ddca (data during conversion additional) can be used.
data sheet ADAS3022 rev. b | page 33 of 40 sampling on the sck rising edge (alternate edge) spi or other alternate edge transfers typically require more time to access data because the total data transfer time of these slower hosts can be > t ddc . if this is the case, the time from t quiet to the next cnv rising edge , which is known as t he data access time after conversion (t dac ) and is determined by the user , must be adjusted by lowering the throughput rat e (cnv frequency) , thus providing the necessary time. if this does not allow en ough time , the data access can be broken up so that some data access occurs during this time followed by the remainder of data access occurring during the next t ddc and t ddca times. cfg readback the cfg result associated with the current conversion can be read back with an additional 16 sck burst following the conversion result (see figure 69) . after the lsb of the conversion result is clocked out, the msb of the cfg associated with th at conversion follows. subsequent sck falling edges repeat the conversion result and cfg word. for example , when cpha is 0 , the msb of the conversion result is output on the 32 nd falling edge . general consideratio ns because the time to access data is somewhat restricted, the following guidelines are useful in determining the ADAS3022 throughput , or cnv frequency, and the serial interface details. note that in figure 70 to figure 72, t ad is for reference purposes only and denotes a time without digital activity because such activity should not occur prior to or just after sampling. data access d uring conversion maximum throughput the maximum throughput rate per channel is determined mainly by the maximum sck period of the host . when using the maximum throughput rate of 1 m sps , the ADAS3022 has an almost symmetric period for both safe data and quiet times (~500 ns each ; see figure 70 ). consequently , t ddc is basically fixed and only provides the host ~500 ns to access data. note that in figure 70, t ad is for reference purposes only and denotes a time without digital activity because such activity should not occur during the sampling edge. for 17 sck edges (worst case), the minimum sck frequency required to achieve a 1 msps (1 s between cnv rising) aggregate throughput rate is mhz 34 17 + ddc ad t t sck f a lthough a dditional time to access data can be attained by trans - ferring data during t ddca , t his is not recommended because the ADAS3022 perform s sensitive bit decisions during this time . if t ddca is used, however, the minimum sck frequency is mhz 25 17 + + ddca ddc ad t t t sck f cs n n n n ? 1 n + 2 n + 2 n + 3 n + 1 n + 1 sdo din sck cnv busy soc eoc t ddc t ad t ddca t quiet 10516-026 figure 70 . data access during conversion data access after / spanning conversion host determined throughput for hosts that do not have the 34 mhz or 25 m hz sck rates available, the maximum throughput rate cannot be achieved because th e data access time after conversion , t dac , must be increased to allow more time to access data. in this case, there are three meth ods to access d ata : ? the first method is to a djust t dac for 17 sck edges (worst case) and the additional cs to cnv setup and hold times. in this case, all data access occurs during t dac . this is the only method that can be used when using a slow host that cannot break up data i nto bytes or other partial data bursts. ? a second method is to break up the data into bursts that can transfer part of the data during t dac of the current conversion and the rest of the data during t ddc of the next conversion. note that cs can stay low thro ughout the cnv rising phase; however, serial clock activity should pause while the input is being sampl ed . ? a third method is to use the second method along with the additional t ddca , again noting that digital activity must cease af ter this time to prevent the current conversion from becoming corrupted. in any of these methods, if the time between conversions (t cyc ) is exceeded for the fastest possible throughput mode (cms = 0), the conversion results will be inaccurate. if this is t he case, the fully asynchronous mode (cms = 1) must be selected (see the conversion modes section for details). figure 71 shows a basic timing diagram for all three methods . for conversion (n), the data is read back after the end of a conversion (n) , with the remainder of data read into the next (n + 1) conversion.
ADAS3022 data sheet rev. b | page 34 of 40 10516-027 cs n n xx n n ? 1 n + 2 n + 3 sdo din sck cnv busy soc soc eoc t ccs t ddc t ddca t ad n + 1 x n + 1 n n + 3 t dac figure 71. data access spanning conversion general timing figure 72 is a general timing diagram showing the complete register to conversion and readback pipeline delay. the figure details the timing upon power-up or upon returning from a full power-down by use of the pd input. figure 73 and figure 74 show the general timing diagrams when only the auxiliary adc input channel pair is enabled for the data read during conversion (rdc) mode and the read after conversion (rac) mode, respectively. 10516-228 acquisition (n) undefined phase power up conversion (n ? 1) undefined cnv busy din cs sdo notes 1. data access can occur during a conversion ( t ddc ), after a conversion ( t dac ), or both during and after a conversion. the conversion result and the cfg regi ster are updated at the end of a conversion (eoc). 2. data access can also occur up to t ddca while busy is active (see the digital interface section for details). all of the busy time can be used to acquire data. 3. a total of 16 sck falling edges is required for a conversion result. an additional 16 edges are required to read back the cfg result associated with the current conversion. 4. cs can be held low or connected to cnv. cs with full independent control is shown in this figure. 5. for optimal performance, data access should not occur during the sampling edge. a minimum time of the aperture delay ( t ad ) should elapse prior to data access. data invalid sck 1 1 1 16/32 16 16 x 16 note 3 note 1 note 2 note 2 note 1 note 4 note 5 cfg invalid cfg (n + 2) data (n ? 1) invalid acquisition (n + 1) undefined conversion (n) undefined data (n ? 1) invalid cfg (n + 2) cfg (n + 3) data (n) invalid acquisition (n + 2) conversion (n + 1) undefined data (n) invalid cfg (n + 3) cfg (n + 4) data (n + 1) invalid acquisition (n + 3) phase conversion (n + 2) cnv busy din cs sdo data (n + 1) invalid sck 1 1 cfg (n + 4) cfg (n + 5) data (n + 2) acquisition (n + 4) conversion (n + 3) data (n + 2) cfg (n + 5) cfg (n + 6) data (n + 3) conversion (n + 4) data (n + 3) cfg (n + 6) eoc eoc eoc eoc eoc soc soc t ddc t cyc t quiet t dac t acq t ad t ddca figure 72. general timing diagram
data sheet ADAS3022 rev. b | page 35 of 40 cs n n n ? 1 n + 2 n + 2 n + 1 n + 1 sdo din sck cnv busy soc eoc t ad t quiet 1 16 n n + 3 n + 2 n + 1 n + 4 11 6 1 16 10516-252 figure 73. general timing diagram of aux input channel pair (rdc) cs n n n n + 2 n + 3 n + 1 n + 1 sdo din sck cnv busy soc eoc t ad t quiet 1 16 1 16 n + 1 n + 4 t en n + 2 1 16 n + 2 n + 5 n + 3 n + 3 10516-253 figure 74. general timing diagram of aux input channel pair (rac)
ADAS3022 data sheet rev. b | page 36 of 40 configuration regist er the configuration register, cfg , is a 16 - bit , programmable register for selecting all of the ADAS3022 user - programmable option s (see table 11) . the register is loaded when data is read back for the first 16 sck rising edges and is updated at the next eoc . n ote that there is always a two - deep delay (n + 2) when writing cfg and w hen reading back cfg for th e setting associated with the current conversion. the default cfg setting is applied when the adas30 22 returns from the reset state (reset = high) to the operational state (reset = low). however, when the ADAS3022 r eturn s from the full power - down state ( pd = high ) to an enabled state (pd = low) , the default cfg setting is not applied, and at least two dummy conversions are required for the user - specified cfg setting to take effect. therefore, the default value is cfg [15:0] = 0x8fcf. this sets the ADAS3022 as follows : ? overwrites contents of cfg register ? selects the in0 input channel referenced to com ? configures the pgia gain to 0.20 ( 20.48 v) ? selects the multiplexer input ? disables the internal channel sequencer ? disables the temperature sensor ? enables the internal reference ? selects n ormal c onve rsion mode ? selects spi interface mode table 10. configuration register, cf g; default value = 0x8fcf (1000 1111 1100 1111) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 cfg inx i nx i nx com rsv pgia pgia pgia mux seq seq temp b refen cms cp ha table 11 . configuration register bit description bits bit name description 1 5 cfg configuration update. 0 = keep current configuration settings. 1 = overwrite contents of registe r (default) . [14:12] inx input channel s election in binary fashion. see the multiplexer section. bit 14 bit 13 bit 12 channel 0 0 0 in0 (default) 1 1 1 in7 11 com in[7:0] common channel input. aux+ and aux? are not referenced to com. 0 = channels are referenced in differential pairs: in0/in1 , in2/in3, in4/in5, and in6/in7 (see the channel sequencer details section ) . 1 = each channel is referenced to a common sense, com (default). 10 rsv reserved. setting or clearing this bit has no effect. [9:7] pgia programmable gain selection (see the input structure section). in basic sequencer modes, this register conf igures the range for all channels. in advanced sequencer mode, this register sets the range for in0 (com = 1) or the in0/in1 pair (com = 0). see the advanced mode section for the pgia configurations of individual channels or channel pairs. bit 9 bit 8 b it 7 absolute input voltage ra nge 0 0 0 24.576 v 0 0 1 10.24 v 0 1 0 5.12 v 0 1 1 2.56 v 1 0 0 1.28 v 1 0 1 0. 64 v 1 1 0 not used 1 1 1 2 0. 48 v (default) 6 mux multiplexer/auxiliary channel input (see the auxiliary input channel section). 0 = selects a uxiliary channel on aux inputs as active channel. 1 = uses the selected analog front end (afe) channel/channel p air (default) .
data sheet ADAS3022 rev. b | page 37 of 40 bits bit name description [5:4] seq channel sequencer. allows for scanning channels seq uentially from in0 to inx . inx is the last channel converted prior to resetting the sequence back to in0 and is specified by the channel selected in the inx[2:0] configuration bits (see the channel sequencer details section ) . bit 5 bit 4 function 0 0 disable sequencer (default) 0 1 update configuration during basic sequence 1 0 initialize advanced sequencer 1 1 initialize basic sequencer 3 temp b temperature sensor enable control (s ee th e c hannel sequencer details section ) . 0 = internal temperature sensor enabled. 1 = internal temperature sensor disabled (default). 2 refen internal reference selection (see the pin configuration and function descriptions and voltage reference input/output sections for more information). 0 = disables the internal reference. the internal reference buffer is disabled by pulling refin to ground. 1 = enables the internal reference ( default ) . 1 cms conversion mode select (se e the conversion modes section). 0 = uses the warp mode for conversions with a time between conversion restriction. 1 = uses the normal mode for conversions ( default ) . 0 cpha msb select (see the c pha section). 0 = asserting cs after the end of a conversion places the msb on sdo, and the first sck falling edge places (msb ? 1) on sdo. 1 = asserting cs after the end of a conversion places the msb on sdo, and the first sck falling edge repeats msb on sdo (default) . channel sequencer details the ADAS3022 includes a channel sequencer, which is useful for scanning channels in a sequential order. channels are scanned individually with reference to com or as pairs and can also include the auxiliary channel pair and/or the internal temperature sensor measurement. after the last programmed measurement is s ampled, the ADAS3022 sequencer is reset to the first channel (in0) or channel pair (in0/in1) and r epeats the sequence until the sequencer is disabled or an asynchronous reset or pd occurs. when the channel sequencer is enabled, for all differential pairs, t he positive terminals are the even channels (in0, in2, in4 , and in6) , and the negative terminals are , conversely , the odd channels (in1, in3, in5 , and in7). when the channel sequencer is disabled, the user can assign either positive or negative terminals to even or odd channels for all differential pairs , depending on the inx [14:12] settings . for exa mple, if inx [14:12] = 00 1 when using the in0/in1 pair , in1 is the positive input and in0 is the negative input. each sequence loop always starts with in0 or in0/in1 and terminates with either the last channel/channel pair set in the inx bits, the temperatu re sensor, or the auxiliary input channel , depending on the configuration word. table 12 provides a quick reference for how the device responds to the programmed configu - ration. for the first case , the channel sequencer scan s cha nnel in0 through channel in3 in a repeated fashion. note that the last conversion is corrupt ed when exiting the sequencer. table 12. typical channel sequencer example inx[ 14:12 ] com mux temp b e nd of sequence 011 1 1 1 in3 (to com) 111 1 1 1 in7 (to com) 11x 0 1 1 in6 to in7 111 1 1 0 temp b 111 1 0 1 aux 111 1 0 0 aux inx and com inputs (mux = 1 , temp b = 1 ) to us e individual inx channels with reference to com or pairs of inx channels in a sequence without converting the aux o r temperature sensor channels, the mux and temp b bits must be set to 1. the last channel to be converted in the sequence is specified by the channel set in the inx bits. after the last channel is scanned, the next conversion start s over at in0 or in0/ in 1. for paired channels, the channels are paired depending on the last channel set in inx. note that the channels are always paired with the positive input on the even channels (in0, in2, in4, in6) and the negative input on the odd channels (in1, in3, in5, in7 ). therefore , setting inx to 110 or 111 scans all pairs with the positive inputs dedicat ed to in0, in2, in4, and in6. for example , to scan four single channels, set inx to 011, com to 1, and mux to 1 , which result s in a sequence order of in0, in1, in2, in3 , in0 , in1, in2, and in3.
ADAS3022 data sheet rev. b | page 38 of 40 inx and com inputs with aux inputs (mux = 0 , tempb = 1) to us e individual inx channels with reference to com or pairs of inx channels with the aux inputs in a sequence , the mux bit must be set to 0 to append the aux channel to the end of the sequence ( after the channel set in inx is scanned ) . note that the aux input is a pair , whereas the inx channel can be referenced to com or pairs of inx channels . for example , to scan four single channels and the aux inputs , set inx to 011, com to 1 , and mux to 0, which result s in a sequence order of in0, in1, in2, in3, aux, in0, in1, in2, in3 , aux , and so on . inx and com inputs with temperature sensor (mux = 1, temp b = 0) to append the temperature sensor conversion to the end of the input chann el sequence , the temp b bit must be set low in the configuration word. n ote that the temperature sensor requires at least 5 s between conversions. the data is output in straight binary format. i nx and com inputs with aux inputs and temperature sensor (mux = 0, temp b = 0) both temperature sensor conversions and auxiliary channel conversions can be appended to the end of the input sequence by setting the mux and temp b bits in the cf g register . for example, to scan all input channels with respect to com, the temperature sensor , and the auxiliary channel at once , the user must set inx to 111 , com to 1, mux to 0 , and temp b to 0. the resulting sequence would be in0, in1, in2, in3, in4, in5, in6, in7, temperature sensor , and aux . sequencer modes the ADAS3022 has two sequencer modes , which are configured with the seq bits : basic mode and advanced mode . b asic mo de can be used whe n all channels are configur ed with the same pgia range. a dvanced mode allows individual channel ranges to be programmed using two additional advanced sequence registers, asr0 and asr1. the seq bits are used to enable the sequencer. settin g seq to 01, 10 , or 11 specifies which sequencer mode is used. depending on the mode, basic or advanced sequencing determines the next data into din. note that for any sequencer update there exists a two - deep delay when writing the register for the setting to take effect. basic sequencer mode ( seq = 11 ) th e basic mode is useful for systems that use the same pgia range on all channels. in basic sequencer mode , all that is required is a single cfg word to place the ADAS3022 in an automatically scanned mode. on the second conversion following the eoc for sequencer cfg, the sequencer starts. after the cfg for basic sequence updates, din must be held low for at least the msb during the data readback or a new cfg word will update , disabling the sequencer. update during sequence (seq = 01 ) some of the cfg setting s, such as pgia and cms, can be updated during a sequence. writing a new cfg word with the appropriate bits to be change d for the (n + 2) conversion update s the sequencer from that point; all channels then use , for example, th e new pgia value . note that changing bits in in x for the las t channel or chang - ing com reinitialize s the sequencer at the (n + 2) conversion. a more practical method is to use the advanced sequencer mode as described in the advanced sequencer mode (seq = 10) section . advanced sequencer mode ( seq = 10 ) the advanced mode is useful for systems that require different gains for different individual inx inputs or different pairs of inx inputs. in this mode, two additional registers are used to program the various gain settings. after the initial cfg word enabling the advanced sequencer mode is written, the ADAS3022 expects to receive at least one additional d ata transfer for the first advanced sequencer register, asr0, or both advanced sequencer registers, depending on how many channels are in the sequence. each asr requires a conversion and a corresponding eoc to load the data into the device. the user cannot simply write 48 bits all at once because, as with all cfg word transfers, only the first 16 bits are latched and updated at eoc. note that the pgia setting for in0 or in0/in1 is written in the initial cfg register, and if using pairs of inx channels, onl y asr0 is required. after the cfg and the associated advanced sequencer registers are updated, din must be held low for at least the msb of subsequent data transfers ; otherwise , the advanced sequencer mode will be aborted. table 13. advanced sequencer register 0 bits function 15 asr 0 write enable 0 = update asr0 following cfg for advanced sequencer 1 = enters normal cfg update [14:11] reserved [10:8] pgia for in1 or in2/ in3 7 reserved [6:4] pgia for in2 or in4/ in 5 3 reserve d [2:0] pgia for in3 or in6/ in 7 table 14 . advanced sequ encer register 1 bits function 15 asr 1 write enable 0 = update asr1 following asr0 1 = enters normal cfg update [14:12] pgia for in4 11 reserved [10:8] pgia for in5 7 reserved [6:4] pgia for in6 3 reserved [2:0] pgia for in7
data sheet ADAS3022 rev. b | page 39 of 40 outline dimensions 07-19-2012-b 0.50 bsc bottom view top view pin 1 indicator exposed pad p i n 1 i n d i c a t o r seating plane 0.05 max 0.02 nom 0.20 ref coplanarity 0.08 0.30 0.25 0.18 6.10 6.00 sq 5.90 1.00 0.95 0.85 for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. 0.45 0.40 0.35 0.25 min * 4.70 4.60 sq 4.50 * compliant to jedec standards mo-220-vjjd-5 with exception to exposed pad dimension. 40 1 11 10 20 21 30 31 figure 75. 40-lead lead frame chip scale package (lfcsp_vq) 6 mm 6 mm body, very thin quad (cp-40-15) dimensions shown in millimeters ordering guide model 1 temperature range package description package option ADAS3022bcpz ?40c to +85c 40-lead lead frame chip scale package (lfcsp_vq) cp-40-15 ADAS3022bcpz-rl7 ?40c to +85c 40-lead lead frame chip scale package (lfcsp_vq) cp-40-15 eval-ADAS3022edz evaluation board 1 z = rohs compliant part.
ADAS3022 data sheet rev. b | page 40 of 40 notes ? 2012 C 2013 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d10516 - 0- 4/13(b)

▲Up To Search▲

Price & Availability of ADAS3022

	To Download ADAS3022 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .